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[PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER
From: |
Cédric Le Goater |
Subject: |
[PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) |
Date: |
Mon, 9 Aug 2021 15:45:37 +0200 |
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB
to be consistent with the other interrupt sources of the system.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 6 ++++++
hw/ppc/pnv_psi.c | 30 ++++++++++++++++++++++++------
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2d7eade23ccc..836147d81e1c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1519,6 +1519,9 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
&error_fatal);
+ /* This is the only device with 4k ESB pages */
+ object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
return;
}
@@ -1770,6 +1773,9 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip10->psi), "bar",
PNV10_PSIHB_BASE(chip), &error_fatal);
+ /* PSI can now be configured to use 64k ESB pages on POWER10 */
+ object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
return;
}
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index cd9a2c5952a6..737486046d5a 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -601,7 +601,6 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB9_IRQ_METHOD PPC_BIT(0)
#define PSIHB9_IRQ_RESET PPC_BIT(1)
#define PSIHB9_ESB_CI_BASE 0x60
-#define PSIHB9_ESB_CI_64K PPC_BIT(1)
#define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)
#define PSIHB9_ESB_CI_VALID PPC_BIT(63)
#define PSIHB9_ESB_NOTIF_ADDR 0x68
@@ -646,6 +645,14 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB9_IRQ_STAT_DIO PPC_BIT(12)
#define PSIHB9_IRQ_STAT_PSU PPC_BIT(13)
+/* P10 register extensions */
+
+#define PSIHB10_CR PSIHB9_CR
+#define PSIHB10_CR_STORE_EOI PPC_BIT(12)
+
+#define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE
+#define PSIHB10_ESB_CI_64K PPC_BIT(1)
+
static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
{
PnvPsi *psi = PNV_PSI(xf);
@@ -704,6 +711,13 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr
addr,
switch (addr) {
case PSIHB9_CR:
+ if (val & PSIHB10_CR_STORE_EOI) {
+ psi9->source.esb_flags |= XIVE_SRC_STORE_EOI;
+ } else {
+ psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI;
+ }
+ break;
+
case PSIHB9_SEMR:
/* FSP stuff */
break;
@@ -715,15 +729,20 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr
addr,
break;
case PSIHB9_ESB_CI_BASE:
+ if (val & PSIHB10_ESB_CI_64K) {
+ psi9->source.esb_shift = XIVE_ESB_64K;
+ } else {
+ psi9->source.esb_shift = XIVE_ESB_4K;
+ }
if (!(val & PSIHB9_ESB_CI_VALID)) {
if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
}
} else {
if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
- memory_region_add_subregion(sysmem,
- val & ~PSIHB9_ESB_CI_VALID,
- &psi9->source.esb_mmio);
+ hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID |
PSIHB10_ESB_CI_64K);
+ memory_region_add_subregion(sysmem, addr,
+ &psi9->source.esb_mmio);
}
}
psi->regs[reg] = val;
@@ -831,6 +850,7 @@ static void pnv_psi_power9_instance_init(Object *obj)
Pnv9Psi *psi = PNV9_PSI(obj);
object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
+ object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift");
}
static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
@@ -839,8 +859,6 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error
**errp)
XiveSource *xsrc = &PNV9_PSI(psi)->source;
int i;
- /* This is the only device with 4k ESB pages */
- object_property_set_int(OBJECT(xsrc), "shift", XIVE_ESB_4K, &error_fatal);
object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS,
&error_fatal);
object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort);
--
2.31.1
- Re: [PATCH 06/26] ppc/pnv: add a chip topology index for POWER10, (continued)
- [PATCH 09/26] ppc/xive2: Introduce a XIVE2 core framework, Cédric Le Goater, 2021/08/09
- [PATCH 14/26] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge, Cédric Le Goater, 2021/08/09
- [PATCH 15/26] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2021/08/09
- [PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10),
Cédric Le Goater <=
- [PATCH 22/26] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2021/08/09
- [PATCH 11/26] ppc/pnv: Add a XIVE2 controller to the POWER10 chip., Cédric Le Goater, 2021/08/09
- [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10, Cédric Le Goater, 2021/08/09
- [PATCH 18/26] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2021/08/09
- [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2021/08/09
- [PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5, Cédric Le Goater, 2021/08/09
- [PATCH 21/26] pnv/xive2: Introduce new capability bits, Cédric Le Goater, 2021/08/09