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[PULL 34/44] hw/intc: openpic: Correct the reset value of IPIDR for FSL
From: |
David Gibson |
Subject: |
[PULL 34/44] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset |
Date: |
Thu, 30 Sep 2021 15:44:16 +1000 |
From: Bin Meng <bmeng.cn@gmail.com>
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:
- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.
Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20210918032653.646370-1-bin.meng@windriver.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/openpic.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 9b4c17854d..2790c6710a 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d)
break;
}
+ /* Mask all IPI interrupts for Freescale OpenPIC */
+ if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
+ (opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
+ if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
+ write_IRQreg_idr(opp, i, 0);
+ continue;
+ }
+ }
+
write_IRQreg_idr(opp, i, opp->idr_reset);
}
/* Initialise IRQ destinations */
--
2.31.1
- [PULL 23/44] target/ppc: add LPCR[HR] to DisasContext and hflags, (continued)
- [PULL 23/44] target/ppc: add LPCR[HR] to DisasContext and hflags, David Gibson, 2021/09/30
- [PULL 24/44] target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l], David Gibson, 2021/09/30
- [PULL 26/44] spapr_numa.c: scrap 'legacy_numa' concept, David Gibson, 2021/09/30
- [PULL 27/44] spapr_numa.c: parametrize FORM1 macros, David Gibson, 2021/09/30
- [PULL 29/44] spapr: move FORM1 verifications to post CAS, David Gibson, 2021/09/30
- [PULL 32/44] target/ppc: Convert debug to trace events (decrementer and IRQ), David Gibson, 2021/09/30
- [PULL 36/44] hw/intc: openpic: Clean up the styles, David Gibson, 2021/09/30
- [PULL 33/44] target/ppc: Fix 64-bit decrementer, David Gibson, 2021/09/30
- [PULL 31/44] spapr_numa.c: handle auto NUMA node with no distance info, David Gibson, 2021/09/30
- [PULL 28/44] spapr_numa.c: rename numa_assoc_array to FORM1_assoc_array, David Gibson, 2021/09/30
- [PULL 34/44] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset,
David Gibson <=
- [PULL 35/44] hw/intc: openpic: Drop Raven related codes, David Gibson, 2021/09/30
- [PULL 30/44] spapr_numa.c: FORM2 NUMA affinity support, David Gibson, 2021/09/30
- [PULL 37/44] spapr_numa.c: fixes in spapr_numa_FORM2_write_rtas_tables(), David Gibson, 2021/09/30
- [PULL 38/44] spapr/xive: Fix kvm_xive_source_reset trace event, David Gibson, 2021/09/30
- [PULL 39/44] MAINTAINERS: Remove machine specific files from ppc TCG CPUs entry, David Gibson, 2021/09/30
- [PULL 40/44] MAINTAINERS: Remove David & Greg as reviewers for a number of boards, David Gibson, 2021/09/30
- [PULL 41/44] MAINTAINERS: Orphan obscure ppc platforms, David Gibson, 2021/09/30
- [PULL 43/44] MAINTAINERS: Add information for OpenPIC, David Gibson, 2021/09/30
- [PULL 42/44] MAINTAINERS: Remove David & Greg as reviewers/co-maintainers of powernv, David Gibson, 2021/09/30
- [PULL 44/44] MAINTAINERS: Demote sPAPR from "Supported" to "Maintained", David Gibson, 2021/09/30