On Tue, 5 Oct 2021, Jesse Millwood wrote:
Thanks for the int suggestion. These tracing flags are really useful. I
added the int one and got the following:
Raise exception at fff80000 => 0000000e (00)
invalid/unsupported opcode: 00 - 00 - 00 - 00 (00000000) 00000000
Raise exception at 00000000 => 00000060 (21)
Raise exception at 00000000 => 00000060 (21)
Raise exception at 00000000 => 00000060 (21)
Raise exception at 00000000 => 00000060 (21)
So it looks like the 0xe is the exception that happens at my pc,
0xfff80000. It looks like that 0xe corresponds to the exception vectors
definitions enum in ppc/cpu.h? So that 0xe would be an instruction tlb
miss? Then the others at 0x60 would be Hypervisor emulation assistance?
That doesn't seem right.
Tho others after invalid instruction don't matter as that's just a result of
trying to execute the non-existent handler for the exception you get first.
Things have gone astray after that so that does not matter any more, the
problem is before that. I'd expect that to result in program exception for
illegal instruction at 0, not sure how you get 0x60 instead but it's already
wrong that it can't get the first instruction so the rest does not really
matter.
Good find with the mmubooke_create_initial_mapping() suggestion. That
function seems to be doing the following:
- ps = 0x10
- size = 0x800 (the ps shifted for the tsize field)
- tlb mmu assist 1
- Looks like it is setting the valid bit and setting the tlb entries to
16KB
- tlb mmu assist 2
- tlb mmu assist 7_3 (I'm not entirely sure why this is 7_3 but I can only
guess this is the mas3 register?)
- Seems to set the User read/write/execute bits and supervisor read,
write, execute bits
It looks like TLBnCFG_N_ENTRY is set to 0xfff
So it looks like I would have 0xfff x 16000 entries? So then would only
65MB of memory be mapped then off the bat?