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[PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running |
Date: |
Sun, 17 Oct 2021 22:01:30 -0300 |
Up until this moment we were assuming that the counter negative
enabled bits, PMC1CE and PMCjCE, would never be changed when the
PMU is already started.
Turns out that there is no such restriction in the PowerISA v3.1,
and software can enable/disable overflow conditions of the counters
at any time.
To support this scenario, track the overflow bits state when a
write in MMCR0 is made in which the run state of the PMU (MMCR0_FC
bit) didn't change and, if some overflow bit were changed in the
middle of a cycle count session, restart it.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/power8-pmu.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 3fc09cebe4..4bd07ba865 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -277,6 +277,30 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong
value)
} else {
start_cycle_count_session(env);
}
+ } else {
+ /*
+ * No change in MMCR0_FC state, but if the PMU is running and
+ * a change in the counter negative overflow bits is made,
+ * we need to restart a new cycle count session to restart
+ * the appropriate overflow timers.
+ */
+ if (curr_FC) {
+ return;
+ }
+
+ bool pmc1ce_curr = curr_value & MMCR0_PMC1CE;
+ bool pmc1ce_new = value & MMCR0_PMC1CE;
+ bool pmcjce_curr = curr_value & MMCR0_PMCjCE;
+ bool pmcjce_new = value & MMCR0_PMCjCE;
+
+ if (pmc1ce_curr == pmc1ce_new && pmcjce_curr == pmcjce_new) {
+ return;
+ }
+
+ /* Update the counter with the events counted so far */
+ pmu_events_update_cycles(env);
+
+ start_cycle_count_session(env);
}
}
--
2.31.1
- [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 01/15] target/ppc: add MMCR0 PMCC bits to hflags, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 04/15] target/ppc: adding user read/write functions for PMCs, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 03/15] target/ppc: add user read/write functions for MMCR2, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 02/15] target/ppc: add user read/write functions for MMCR0, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 06/15] target/ppc: initialize PMUEvents on MMCR1 write, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 05/15] target/ppc: introduce PMU events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 08/15] target/ppc: enable PMU counter overflow with cycle events, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 07/15] target/ppc: PMU basic cycle count for pseries TCG, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 12/15] target/ppc/power8-pmu.c: handle overflow bits when PMU is running,
Daniel Henrique Barboza <=
- [PATCH v4 14/15] target/ppc: PMU Event-Based exception support, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 09/15] target/ppc: enable PMU instruction count, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 11/15] target/ppc: PMU: handle setting of PMCs while running, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 10/15] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 15/15] target/ppc/excp_helper.c: EBB handling adjustments, Daniel Henrique Barboza, 2021/10/17
- [PATCH v4 13/15] PPC64/TCG: Implement 'rfebb' instruction, Daniel Henrique Barboza, 2021/10/17
- Re: [PATCH v4 00/15] PPC64/TCG: Implement 'rfebb' instruction, David Gibson, 2021/10/17