[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP
From: |
matheus . ferst |
Subject: |
[PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP |
Date: |
Thu, 4 Nov 2021 09:37:11 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxvp and pstxvp using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 9 +++++++++
target/ppc/translate/vsx-impl.c.inc | 2 ++
2 files changed, 11 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 093439b370..880ac3edc7 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -27,6 +27,11 @@
..... rt:6 ra:5 ................ \
&PLS_D si=%pls_si
+%rt_tsxp 21:1 22:4 !function=times_2
+@8LS_D_TSXP ...... .. . .. r:1 .. .................. \
+ ...... ..... ra:5 ................ \
+ &PLS_D si=%pls_si rt=%rt_tsxp
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -147,3 +152,7 @@ PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
11011 ...... ..... ................ @8LS_D_TSX
+PLXVP 000001 00 0--.-- .................. \
+ 111010 ..... ..... ................ @8LS_D_TSXP
+PSTXVP 000001 00 0--.-- .................. \
+ 111110 ..... ..... ................ @8LS_D_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 1972127a22..6c60e29cca 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2060,6 +2060,8 @@ TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
TRANS64(PLXV, do_lstxv_PLS_D, false, false)
+TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
+TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.25.1
- [PATCH v3 06/25] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, (continued)
- [PATCH v3 06/25] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, matheus . ferst, 2021/11/04
- [PATCH v3 09/25] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, matheus . ferst, 2021/11/04
- [PATCH v3 10/25] target/ppc: Introduce REQUIRE_VSX macro, matheus . ferst, 2021/11/04
- [PATCH v3 08/25] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 11/25] target/ppc: receive high/low as argument in get/set_cpu_vsr, matheus . ferst, 2021/11/04
- [PATCH v3 12/25] target/ppc: moved stxv and lxv from legacy to decodtree, matheus . ferst, 2021/11/04
- [PATCH v3 13/25] target/ppc: moved stxvx and lxvx from legacy to decodtree, matheus . ferst, 2021/11/04
- [PATCH v3 15/25] target/ppc: added the instructions LXVPX and STXVPX, matheus . ferst, 2021/11/04
- [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP, matheus . ferst, 2021/11/04
- [PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV, matheus . ferst, 2021/11/04
- [PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP,
matheus . ferst <=
- [PATCH v3 19/25] target/ppc: moved XXSPLTIB to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 18/25] target/ppc: moved XXSPLTW to using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 20/25] target/ppc: implemented XXSPLTI32DX, matheus . ferst, 2021/11/04
- [PATCH v3 21/25] target/ppc: Implemented XXSPLTIW using decodetree, matheus . ferst, 2021/11/04
- [PATCH v3 22/25] target/ppc: implemented XXSPLTIDP instruction, matheus . ferst, 2021/11/04
- [PATCH v3 23/25] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, matheus . ferst, 2021/11/04
- [PATCH v3 24/25] target/ppc: Implement lxvkq instruction, matheus . ferst, 2021/11/04
- [PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond, matheus . ferst, 2021/11/04
- Re: [PATCH v3 00/25] PowerISA v3.1 instruction batch, David Gibson, 2021/11/04