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[PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR inde
From: |
David Gibson |
Subject: |
[PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns |
Date: |
Tue, 9 Nov 2021 16:51:44 +1100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index
vinshvlx: Vector Insert Halfword from VSR using GPR-specified
Left-Index
vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index
vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index
vinshvrx: Vector Insert Halfword from VSR using GPR-specified
Right-Index
vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-8-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 7 +++++++
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e1f76aac34..de410abf7d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -359,5 +359,12 @@ VINSDRX 000100 ..... ..... ..... 01111001111 @VX
VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+VINSBVLX 000100 ..... ..... ..... 00000001111 @VX
+VINSBVRX 000100 ..... ..... ..... 00100001111 @VX
+VINSHVLX 000100 ..... ..... ..... 00001001111 @VX
+VINSHVRX 000100 ..... ..... ..... 00101001111 @VX
+VINSWVLX 000100 ..... ..... ..... 00010001111 @VX
+VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 9642cfa037..46d6890242 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1260,6 +1260,20 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int
size, bool right, TCGv ra,
return true;
}
+static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv
ra,
+ int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64,
TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ val = tcg_temp_new_i64();
+ get_avr64(val, vrb, true);
+ ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1278,6 +1292,16 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a,
int size, bool right,
return ok;
}
+static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
+ gen_helper);
+}
+
static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1325,6 +1349,14 @@ TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
+
+TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.33.1
- [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents, (continued)
- [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents, David Gibson, 2021/11/09
- [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions, David Gibson, 2021/11/09
- [PULL 06/54] target/ppc: Implement PLQ and PSTQ, David Gibson, 2021/11/09
- [PULL 17/54] target/ppc: Implement DCTFIXQQ, David Gibson, 2021/11/09
- [PULL 18/54] target/ppc: Do not update nip on DFP instructions, David Gibson, 2021/11/09
- [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr, David Gibson, 2021/11/09
- [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree, David Gibson, 2021/11/09
- [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, David Gibson, 2021/11/09
- [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns,
David Gibson <=
- [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled, David Gibson, 2021/11/09
- [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions, David Gibson, 2021/11/09
- [PULL 13/54] target/ppc: Introduce REQUIRE_FPU, David Gibson, 2021/11/09
- [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree, David Gibson, 2021/11/09
- [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction, David Gibson, 2021/11/09
- [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, David Gibson, 2021/11/09
- [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns, David Gibson, 2021/11/09
- [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree, David Gibson, 2021/11/09
- [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, David Gibson, 2021/11/09