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[PULL 47/54] target/ppc: implemented XXSPLTI32DX
From: |
David Gibson |
Subject: |
[PULL 47/54] target/ppc: implemented XXSPLTI32DX |
Date: |
Tue, 9 Nov 2021 16:51:57 +1100 |
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented XXSPLTI32DX emulation using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-21-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 11 +++++++++++
target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3edc7..134bc60c57 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
+# Format 8RR:D
+%8rr_si 32:s16 0:16
+%8rr_xt 16:1 21:5
+&8RR_D_IX xt ix si
+@8RR_D_IX ...... .. .... .. .. ................ \
+ ...... ..... ... ix:1 . ................ \
+ &8RR_D_IX si=%8rr_si xt=%8rr_xt
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -156,3 +164,6 @@ PLXVP 000001 00 0--.-- .................. \
111010 ..... ..... ................ @8LS_D_TSXP
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+
+XXSPLTI32DX 000001 01 0000 -- -- ................ \
+ 100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index ad25a0daf0..360593a9ab 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,23 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8
*a)
return true;
}
+static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
+{
+ TCGv_i32 imm;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ imm = tcg_constant_i32(a->si);
+
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.33.1
- [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, (continued)
- [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree, David Gibson, 2021/11/09
- [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro, David Gibson, 2021/11/09
- [PULL 40/54] target/ppc: moved stxvx and lxvx from legacy to decodtree, David Gibson, 2021/11/09
- [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree, David Gibson, 2021/11/09
- [PULL 41/54] target/ppc: added the instructions LXVP and STXVP, David Gibson, 2021/11/09
- [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX, David Gibson, 2021/11/09
- [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction, David Gibson, 2021/11/09
- [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV, David Gibson, 2021/11/09
- [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP, David Gibson, 2021/11/09
- [PULL 46/54] target/ppc: moved XXSPLTIB to using decodetree, David Gibson, 2021/11/09
- [PULL 47/54] target/ppc: implemented XXSPLTI32DX,
David Gibson <=
- [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree, David Gibson, 2021/11/09
- [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, David Gibson, 2021/11/09
- [PULL 53/54] target/ppc, hw/ppc: Change maintainers, David Gibson, 2021/11/09
- [PULL 51/54] target/ppc: Implement lxvkq instruction, David Gibson, 2021/11/09
- [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond, David Gibson, 2021/11/09
- [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info, David Gibson, 2021/11/09
- Re: [PULL 00/54] ppc-for-6.2 queue 20211109, Richard Henderson, 2021/11/09