[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 36/41] target/ppc: 74xx: External interrupt cleanup
From: |
Cédric Le Goater |
Subject: |
[PULL 36/41] target/ppc: 74xx: External interrupt cleanup |
Date: |
Mon, 31 Jan 2022 12:08:06 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
The 74xx don't have MSR_HV so all the LPES0 logic can be removed.
Also remove the BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 38 --------------------------------------
1 file changed, 38 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0d8c66b98fd3..b9a1d7ae7e40 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -555,7 +555,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
@@ -625,44 +624,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.34.1
[PULL 36/41] target/ppc: 74xx: External interrupt cleanup,
Cédric Le Goater <=
[PULL 31/41] target/ppc: books: External interrupt cleanup, Cédric Le Goater, 2022/01/31
[PULL 28/41] target/ppc: Introduce powerpc_excp_books, Cédric Le Goater, 2022/01/31
[PULL 39/41] target/ppc: 74xx: System Reset interrupt cleanup, Cédric Le Goater, 2022/01/31
[PULL 15/41] target/ppc: 405: Add missing MSR_ME bit, Cédric Le Goater, 2022/01/31
[PULL 37/41] target/ppc: 74xx: Program exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 17/41] target/ppc: Simplify powerpc_excp_40x, Cédric Le Goater, 2022/01/31
[PULL 22/41] target/ppc: 405: Alignment exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 21/41] target/ppc: 405: System call exception cleanup, Cédric Le Goater, 2022/01/31
[PULL 34/41] target/ppc: Simplify powerpc_excp_74xx, Cédric Le Goater, 2022/01/31
[PULL 09/41] spapr.c: check bus != NULL in spapr_get_fw_dev_path(), Cédric Le Goater, 2022/01/31