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[PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers
From: |
Cédric Le Goater |
Subject: |
[PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers |
Date: |
Fri, 18 Feb 2022 11:38:24 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:
register_sdr1_sprs | 22 callers
register_low_BATs | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs | 10 callers
register_thrm_sprs | 8 callers
register_usprgh_sprs | 6 callers
register_6xx_7xx_soft_tlb | only 3 callers, but it helps to
keep the soft TLB code consistent.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/spr_common.h | 8 ++++++++
target/ppc/cpu_init.c | 14 +++++++-------
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 5aec76ade4dd..329b7e91a23a 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
#endif
+void register_low_BATs(CPUPPCState *env);
+void register_high_BATs(CPUPPCState *env);
+void register_sdr1_sprs(CPUPPCState *env);
+void register_thrm_sprs(CPUPPCState *env);
+void register_usprgh_sprs(CPUPPCState *env);
+void register_non_embedded_sprs(CPUPPCState *env);
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
+
#endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f0bbe340e4fd..40dd2c0fd813 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000);
}
-static void register_non_embedded_sprs(CPUPPCState *env)
+void register_non_embedded_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env)
}
/* Storage Description Register 1 */
-static void register_sdr1_sprs(CPUPPCState *env)
+void register_sdr1_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) {
@@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env)
}
/* BATs 0-3 */
-static void register_low_BATs(CPUPPCState *env)
+void register_low_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
@@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env)
}
/* BATs 4-7 */
-static void register_high_BATs(CPUPPCState *env)
+void register_high_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
@@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env)
}
/* Softare table search registers */
-static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int
nb_ways)
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static void register_thrm_sprs(CPUPPCState *env)
+void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
spr_register(env, SPR_THRM1, "THRM1",
@@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_usprgh_sprs(CPUPPCState *env)
+void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS,
--
2.34.1
- [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 SPR registration, (continued)
- [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 02/39] spapr: nvdimm: Implement H_SCM_FLUSH hcall, Cédric Le Goater, 2022/02/18
- [PULL 28/39] target/ppc: cpu_init: Move e300 SPR registration into a function, Cédric Le Goater, 2022/02/18
- [PULL 30/39] target/ppc: cpu_init: Reuse init_proc_603 for the e300, Cédric Le Goater, 2022/02/18
- [PULL 03/39] spapr: nvdimm: Introduce spapr-nvdimm device, Cédric Le Goater, 2022/02/18
- [PULL 11/39] target/ppc: Introduce a vhyp framework for nested HV support, Cédric Le Goater, 2022/02/18
- [PULL 34/39] target/ppc: cpu_init: Remove register_usprg3_sprs, Cédric Le Goater, 2022/02/18
- [PULL 25/39] target/ppc: cpu_init: Deduplicate 745/755 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx, Cédric Le Goater, 2022/02/18
- [PULL 22/39] target/ppc: cpu_init: Deduplicate 440 SPR registration, Cédric Le Goater, 2022/02/18
- [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers,
Cédric Le Goater <=
- [PULL 35/39] target/ppc: Rename spr_tcg.h to spr_common.h, Cédric Le Goater, 2022/02/18
- [PULL 05/39] spapr: prevent hdec timer being set up under virtual hypervisor, Cédric Le Goater, 2022/02/18
- [PULL 09/39] target/ppc: add helper for books vhyp hypercall handler, Cédric Le Goater, 2022/02/18
- [PULL 32/39] target/ppc: cpu_init: Reuse init_proc_745 for the 755, Cédric Le Goater, 2022/02/18
- [PULL 33/39] target/ppc: cpu_init: Rename register_ne_601_sprs, Cédric Le Goater, 2022/02/18
- [PULL 20/39] target/ppc: cpu_init: Decouple G2 SPR registration from 755, Cédric Le Goater, 2022/02/18
- [PULL 12/39] spapr: implement nested-hv capability for the virtual hypervisor, Cédric Le Goater, 2022/02/18
- [PULL 31/39] target/ppc: cpu_init: Reuse init_proc_604 for the 604e, Cédric Le Goater, 2022/02/18
- [PULL 15/39] target/ppc: cpu_init: Group registration of generic SPRs, Cédric Le Goater, 2022/02/18
- [PULL 27/39] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function, Cédric Le Goater, 2022/02/18