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[PATCH v4 36/47] target/ppc: Implement xvtlsbb instruction
From: |
matheus . ferst |
Subject: |
[PATCH v4 36/47] target/ppc: Implement xvtlsbb instruction |
Date: |
Tue, 22 Feb 2022 11:36:34 -0300 |
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 7 ++++++
target/ppc/translate/vsx-impl.c.inc | 37 +++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1395a91c44..2617ab8ca4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -155,6 +155,9 @@
&XX2 xt xb uim:uint8_t
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt
xb=%xx_xb
+&XX2_bf_xb bf xb
+@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb
xb=%xx_xb
+
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt
xa=%xx_xa xb=%xx_xb
@@ -664,6 +667,10 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ...
@XX3
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+## VSX Vector Test Least-Significant Bit by Byte Instruction
+
+XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb
+
### rfebb
&XL_s s:uint8_t
@XL_s ......-------------- s:1 .......... - &XL_s
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 9128407365..2aecaa8021 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1690,6 +1690,43 @@ static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
return true;
}
+static bool trans_XVTLSBB(DisasContext *ctx, arg_XX2_bf_xb *a)
+{
+ TCGv_i64 xb, tmp, all_true, all_false, mask, zero;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ xb = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+ all_true = tcg_const_i64(0b1000);
+ all_false = tcg_const_i64(0b0010);
+ mask = tcg_constant_i64(dup_const(MO_8, 1));
+ zero = tcg_constant_i64(0);
+
+ for (int dw = 0; dw < 2; dw++) {
+ get_cpu_vsr(xb, a->xb, dw);
+
+ tcg_gen_and_i64(tmp, mask, xb);
+ tcg_gen_movcond_i64(TCG_COND_EQ, all_true, tmp,
+ mask, all_true, zero);
+
+ tcg_gen_andc_i64(tmp, mask, xb);
+ tcg_gen_movcond_i64(TCG_COND_EQ, all_false, tmp,
+ mask, all_false, zero);
+ }
+
+ tcg_gen_or_i64(tmp, all_false, all_true);
+ tcg_gen_extrl_i64_i32(cpu_crf[a->bf], tmp);
+
+ tcg_temp_free_i64(xb);
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(all_true);
+ tcg_temp_free_i64(all_false);
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.25.1
- [PATCH v4 31/47] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i, (continued)
- [PATCH v4 31/47] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i, matheus . ferst, 2022/02/22
- [PATCH v4 32/47] target/ppc: Implement xxeval, matheus . ferst, 2022/02/22
- [PATCH v4 33/47] target/ppc: Implement xxgenpcv[bhwd]m instruction, matheus . ferst, 2022/02/22
- [PATCH v4 34/47] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 35/47] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], matheus . ferst, 2022/02/22
- [PATCH v4 36/47] target/ppc: Implement xvtlsbb instruction,
matheus . ferst <=
- [PATCH v4 37/47] target/ppc: Remove xscmpnedp instruction, matheus . ferst, 2022/02/22
- [PATCH v4 38/47] target/ppc: Refactor VSX_SCALAR_CMP_DP, matheus . ferst, 2022/02/22
- [PATCH v4 39/47] target/ppc: Implement xscmp{eq,ge,gt}qp, matheus . ferst, 2022/02/22
- [PATCH v4 41/47] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3, matheus . ferst, 2022/02/22