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[PATCH v5 20/49] target/ppc: implement vslq
From: |
matheus . ferst |
Subject: |
[PATCH v5 20/49] target/ppc: implement vslq |
Date: |
Fri, 25 Feb 2022 18:09:07 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 88baebe35e..3799065508 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -473,6 +473,7 @@ VSLB 000100 ..... ..... ..... 00100000100 @VX
VSLH 000100 ..... ..... ..... 00101000100 @VX
VSLW 000100 ..... ..... ..... 00110000100 @VX
VSLD 000100 ..... ..... ..... 10111000100 @VX
+VSLQ 000100 ..... ..... ..... 00100000101 @VX
VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 1b05b0b3a3..49c722e862 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16,
tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ n = tcg_temp_new_i64();
+ hi = tcg_temp_new_i64();
+ lo = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+
+ get_avr64(lo, a->vra, false);
+ get_avr64(hi, a->vra, true);
+
+ get_avr64(n, a->vrb, true);
+
+ tcg_gen_andi_i64(t0, n, 64);
+ tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
+ tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
+ tcg_gen_andi_i64(n, n, 0x3F);
+
+ tcg_gen_shl_i64(t0, lo, n);
+ set_avr64(a->vrt, t0, false);
+
+ tcg_gen_shl_i64(hi, hi, n);
+ tcg_gen_xori_i64(n, n, 63);
+ tcg_gen_shr_i64(lo, lo, n);
+ tcg_gen_shri_i64(lo, lo, 1);
+ tcg_gen_or_i64(hi, hi, lo);
+ set_avr64(a->vrt, hi, true);
+
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(lo);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(n);
+
+ return true;
+}
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.25.1
- [PATCH v5 11/49] target/ppc: Implement Vector Compare Equal Quadword, (continued)
- [PATCH v5 11/49] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/02/25
- [PATCH v5 12/49] target/ppc: Implement Vector Compare Greater Than Quadword, matheus . ferst, 2022/02/25
- [PATCH v5 13/49] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/02/25
- [PATCH v5 15/49] target/ppc: implement vclrlb, matheus . ferst, 2022/02/25
- [PATCH v5 14/49] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/02/25
- [PATCH v5 16/49] target/ppc: implement vclrrb, matheus . ferst, 2022/02/25
- [PATCH v5 17/49] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/02/25
- [PATCH v5 19/49] target/ppc: move vs[lr][a][bhwd] to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 18/49] target/ppc: implement vgnb, matheus . ferst, 2022/02/25
- [PATCH v5 21/49] target/ppc: implement vsrq, matheus . ferst, 2022/02/25
- [PATCH v5 20/49] target/ppc: implement vslq,
matheus . ferst <=
- [PATCH v5 22/49] target/ppc: implement vsraq, matheus . ferst, 2022/02/25
- [PATCH v5 23/49] target/ppc: move vrl[bhwd] to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 24/49] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 25/49] target/ppc: implement vrlq, matheus . ferst, 2022/02/25
- [PATCH v5 27/49] target/ppc: implement vrlqmi, matheus . ferst, 2022/02/25
- [PATCH v5 26/49] target/ppc: implement vrlqnm, matheus . ferst, 2022/02/25
- [PATCH v5 28/49] target/ppc: Move vsel and vperm/vpermr to decodetree, matheus . ferst, 2022/02/25