+#define XXGENPCV(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
+{ \
+ TCGv_ptr xt, vrb; \
+ \
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
+ REQUIRE_VSX(ctx); \
+ \
+ if (a->imm & ~0x3) { \
+ gen_invalid(ctx); \
+ return true; \
+ } \
+ \
+ xt = gen_vsr_ptr(a->xt); \
+ vrb = gen_avr_ptr(a->vrb); \
+ \
+ switch (a->imm) { \
+ case 0b00000: /* Big-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
+ break; \
+ case 0b00001: /* Big-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
+ break; \
+ case 0b00010: /* Little-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
+ break; \
+ case 0b00011: /* Little-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
+ break; \
+ } \
+ \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(vrb); \
+ \
+ return true; \
+}
+
+XXGENPCV(XXGENPCVBM)
+XXGENPCV(XXGENPCVHM)
+XXGENPCV(XXGENPCVWM)
+XXGENPCV(XXGENPCVDM)
+#undef XXGENPCV