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[PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c
From: |
Cédric Le Goater |
Subject: |
[PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c |
Date: |
Wed, 2 Mar 2022 12:06:42 +0100 |
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This patch adds the EBB exception support that are triggered by
Performance Monitor alerts. This happens when a Performance Monitor
alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper
which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits
are set, do_ebb() will attempt to trigger a PERFM EBB event.
If the EBB facility is enabled in both FSCR and HFSCR we consider that
the EBB is valid and set BESCR_PMEO. After that, if we're running in
problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll
queue a PPC_INTERRUPT_EBB.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 5 +++++
target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++
target/ppc/power8-pmu.c | 3 +--
3 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 79375e8df489..1b687521c76c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2502,6 +2502,11 @@ void QEMU_NORETURN raise_exception_err(CPUPPCState *env,
uint32_t exception,
void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
uint32_t error_code, uintptr_t
raddr);
+/* PERFM EBB helper*/
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+void raise_ebb_perfm_exception(CPUPPCState *env);
+#endif
+
#if !defined(CONFIG_USER_ONLY)
static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5e7d29ae0081..d3e2cfcd7120 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2066,6 +2066,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
env->spr[SPR_BESCR] &= ~BESCR_GE;
}
}
+
+/*
+ * Triggers or queues an 'ebb_excp' EBB exception. All checks
+ * but FSCR, HFSCR and msr_pr must be done beforehand.
+ *
+ * PowerISA v3.1 isn't clear about whether an EBB should be
+ * postponed or cancelled if the EBB facility is unavailable.
+ * Our assumption here is that the EBB is cancelled if both
+ * FSCR and HFSCR EBB facilities aren't available.
+ */
+static void do_ebb(CPUPPCState *env, int ebb_excp)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ CPUState *cs = CPU(cpu);
+
+ /*
+ * FSCR_EBB and FSCR_IC_EBB are the same bits used with
+ * HFSCR.
+ */
+ helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB);
+ helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB);
+
+ if (ebb_excp == POWERPC_EXCP_PERFM_EBB) {
+ env->spr[SPR_BESCR] |= BESCR_PMEO;
+ } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) {
+ env->spr[SPR_BESCR] |= BESCR_EEO;
+ }
+
+ if (msr_pr == 1) {
+ powerpc_excp(cpu, ebb_excp);
+ } else {
+ env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
+void raise_ebb_perfm_exception(CPUPPCState *env)
+{
+ bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE &&
+ env->spr[SPR_BESCR] & BESCR_PME &&
+ env->spr[SPR_BESCR] & BESCR_GE;
+
+ if (!perfm_ebb_enabled) {
+ return;
+ }
+
+ do_ebb(env, POWERPC_EXCP_PERFM_EBB);
+}
#endif
/*****************************************************************************/
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index d24566315872..beeab5c494e1 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
}
- /* PMC interrupt not implemented yet */
- return;
+ raise_ebb_perfm_exception(env);
}
/* This helper assumes that the PMC is running. */
--
2.34.1
- [PULL 00/87] ppc queue, Cédric Le Goater, 2022/03/02
- [PULL 04/87] target/ppc: finalize pre-EBB PMU logic, Cédric Le Goater, 2022/03/02
- [PULL 03/87] target/ppc: make power8-pmu.c CONFIG_TCG only, Cédric Le Goater, 2022/03/02
- [PULL 07/87] target/ppc: Introduce TRANS*FLAGS macros, Cédric Le Goater, 2022/03/02
- [PULL 05/87] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions, Cédric Le Goater, 2022/03/02
- [PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c,
Cédric Le Goater <=
- [PULL 02/87] ppc/pnv: fix default PHB4 QOM hierarchy, Cédric Le Goater, 2022/03/02
- [PULL 01/87] hw/ppc/pnv: Determine ns16550's IRQ number from QOM property, Cédric Le Goater, 2022/03/02
- [PULL 13/87] target/ppc: Move vexts[bhw]2[wd] to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 08/87] target/ppc: moved vector even and odd multiplication to decodetree, Cédric Le Goater, 2022/03/02
- [PULL 12/87] target/ppc: Implement vmsumudm instruction, Cédric Le Goater, 2022/03/02
- [PULL 19/87] target/ppc: Implement Vector Compare Quadword, Cédric Le Goater, 2022/03/02
- [PULL 17/87] target/ppc: Implement Vector Compare Equal Quadword, Cédric Le Goater, 2022/03/02
- [PULL 10/87] target/ppc: vmulh* instructions without helpers, Cédric Le Goater, 2022/03/02
- [PULL 14/87] target/ppc: Implement vextsd2q, Cédric Le Goater, 2022/03/02
- [PULL 21/87] target/ppc: implement vclrlb, Cédric Le Goater, 2022/03/02