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[PULL 02/13] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfs
From: |
Cédric Le Goater |
Subject: |
[PULL 02/13] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf |
Date: |
Sat, 5 Mar 2022 11:59:59 +0100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
LLVM/Clang does not support __builtin_mtfsf.
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220304165417.1981159-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/tcg/ppc64le/mtfsf.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c
index b3d31f3637d9..bed5b1afa40e 100644
--- a/tests/tcg/ppc64le/mtfsf.c
+++ b/tests/tcg/ppc64le/mtfsf.c
@@ -1,8 +1,12 @@
#include <stdlib.h>
+#include <stdint.h>
#include <assert.h>
#include <signal.h>
#include <sys/prctl.h>
+#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB))
+#define MFFS(FRT) asm("mffs %0" : "=f" (FRT))
+
#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
#define FPSCR_FI 17 /* Floating-point fraction inexact */
@@ -21,10 +25,7 @@ void sigfpe_handler(int sig, siginfo_t *si, void *ucontext)
int main(void)
{
- union {
- double d;
- long long ll;
- } fpscr;
+ uint64_t fpscr;
struct sigaction sa = {
.sa_sigaction = sigfpe_handler,
@@ -40,10 +41,9 @@ int main(void)
prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE);
/* First test if the FI bit is being set correctly */
- fpscr.ll = FP_FI;
- __builtin_mtfsf(0b11111111, fpscr.d);
- fpscr.d = __builtin_mffs();
- assert((fpscr.ll & FP_FI) != 0);
+ MTFSF(0b11111111, FP_FI);
+ MFFS(fpscr);
+ assert((fpscr & FP_FI) != 0);
/* Then test if the deferred exception is being called correctly */
sigaction(SIGFPE, &sa, NULL);
@@ -54,8 +54,7 @@ int main(void)
* But if a different exception is chosen si_code check should
* change accordingly.
*/
- fpscr.ll = FP_VE | FP_VXSOFT;
- __builtin_mtfsf(0b11111111, fpscr.d);
+ MTFSF(0b11111111, FP_VE | FP_VXSOFT);
return 1;
}
--
2.34.1
- [PULL 00/13] ppc queue, Cédric Le Goater, 2022/03/05
- [PULL 01/13] Use long endian options for ppc64, Cédric Le Goater, 2022/03/05
- [PULL 02/13] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf,
Cédric Le Goater <=
- [PULL 07/13] target/ppc: Fix vmul[eo]* instructions marked 2.07, Cédric Le Goater, 2022/03/05
- [PULL 05/13] tests/tcg/ppc64le: emit bcdsub with .long when needed, Cédric Le Goater, 2022/03/05
- [PULL 09/13] target/ppc: use extract/extract2 to create vrlqnm mask, Cédric Le Goater, 2022/03/05
- [PULL 08/13] target/ppc: use ext32u and deposit in do_vx_vmulhw_i64, Cédric Le Goater, 2022/03/05
- [PULL 11/13] target/ppc: split XXGENPCV macros for readability, Cédric Le Goater, 2022/03/05
- [PULL 12/13] target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINC, Cédric Le Goater, 2022/03/05
- [PULL 10/13] target/ppc: use andc in vrlqmi, Cédric Le Goater, 2022/03/05
- [PULL 13/13] target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16, Cédric Le Goater, 2022/03/05
- [PULL 06/13] tests/tcg/ppc64le: Use Altivec register names in clobber list, Cédric Le Goater, 2022/03/05
- [PULL 03/13] target/ppc: change xs[n]madd[am]sp to use float64r32_muladd, Cédric Le Goater, 2022/03/05