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[PULL 30/30] target/ppc: Check page dir/table base alignment
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 30/30] target/ppc: Check page dir/table base alignment |
Date: |
Mon, 18 Jul 2022 14:22:08 -0300 |
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
According to PowerISA 3.1B, Book III 6.7.6 programming note, the
page directory base addresses are expected to be aligned to their
size. Real hardware seems to rely on that and will access the
wrong address if they are misaligned. This results in a
translation failure even if the page tables seem to be properly
populated.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220628133959.15131-4-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/mmu-radix64.c | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 705bff76be..00f2e9fa2e 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -265,7 +265,7 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr
eaddr,
uint64_t *pte_addr, uint64_t *nls,
int *psize, uint64_t *pte, int *fault_cause)
{
- uint64_t index, pde;
+ uint64_t index, mask, nlb, pde;
/* Read page <directory/table> entry from guest address space */
pde = ldq_phys(as, *pte_addr);
@@ -280,7 +280,17 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr
eaddr,
*nls = pde & R_PDE_NLS;
index = eaddr >> (*psize - *nls); /* Shift */
index &= ((1UL << *nls) - 1); /* Mask */
- *pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde));
+ nlb = pde & R_PDE_NLB;
+ mask = MAKE_64BIT_MASK(0, *nls + 3);
+
+ if (nlb & mask) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: misaligned page dir/table base: 0x"TARGET_FMT_lx
+ " page dir size: 0x"TARGET_FMT_lx"\n",
+ __func__, nlb, mask + 1);
+ nlb &= ~mask;
+ }
+ *pte_addr = nlb + index * sizeof(pde);
}
return 0;
}
@@ -294,8 +304,18 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr
eaddr,
int level = 0;
index = eaddr >> (*psize - nls); /* Shift */
- index &= ((1UL << nls) - 1); /* Mask */
- *pte_addr = base_addr + (index * sizeof(pde));
+ index &= ((1UL << nls) - 1); /* Mask */
+ mask = MAKE_64BIT_MASK(0, nls + 3);
+
+ if (base_addr & mask) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: misaligned page dir base: 0x"TARGET_FMT_lx
+ " page dir size: 0x"TARGET_FMT_lx"\n",
+ __func__, base_addr, mask + 1);
+ base_addr &= ~mask;
+ }
+ *pte_addr = base_addr + index * sizeof(pde);
+
do {
int ret;
--
2.36.1
- [PULL 20/30] target/ppc: Move slbia to decodetree, (continued)
- [PULL 20/30] target/ppc: Move slbia to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 18/30] target/ppc: Move slbie to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 22/30] target/ppc: Move slbmfev to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 23/30] target/ppc: Move slbmfee to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 24/30] target/ppc: Move slbfee to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 17/30] target/ppc: add macros to check privilege level, Daniel Henrique Barboza, 2022/07/18
- [PULL 21/30] target/ppc: Move slbmte to decodetree, Daniel Henrique Barboza, 2022/07/18
- [PULL 26/30] target/ppc: Implement slbiag, Daniel Henrique Barboza, 2022/07/18
- [PULL 28/30] ppc: Check partition and process table alignment, Daniel Henrique Barboza, 2022/07/18
- [PULL 29/30] target/ppc: Improve Radix xlate level validation, Daniel Henrique Barboza, 2022/07/18
- [PULL 30/30] target/ppc: Check page dir/table base alignment,
Daniel Henrique Barboza <=
- [PULL 27/30] target/ppc: check tb_env != 0 before printing TBU/TBL/DECR, Daniel Henrique Barboza, 2022/07/18
- [PULL 25/30] target/ppc: Move slbsync to decodetree, Daniel Henrique Barboza, 2022/07/18
- Re: [PULL 00/30] ppc queue, Peter Maydell, 2022/07/19