[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 17/22] ppc/ppc405: QOM'ify PLB
From: |
Cédric Le Goater |
Subject: |
[PATCH v3 17/22] ppc/ppc405: QOM'ify PLB |
Date: |
Mon, 8 Aug 2022 12:27:29 +0200 |
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 14 +++++++++--
hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++---------------------
hw/ppc/sam460ex.c | 4 +++-
3 files changed, 47 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4140e811d5ec..cb34792daf6b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -232,11 +243,10 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+ Ppc405PlbState plb;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-void ppc4xx_plb_init(CPUPPCState *env);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1e731f69932c..12d25cfbf38b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
uint32_t ret;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,34 @@ static void dcr_write_plb (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *opaque)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_plb_t *plb;
-
- plb = g_new0(ppc4xx_plb_t, 1);
- ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, PLB3A0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_ACR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BEAR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BESR, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A1_ACR, &dcr_read_plb, &dcr_write_plb);
+}
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_plb_reset;
}
/*****************************************************************************/
@@ -1360,6 +1357,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
+
+ object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1385,7 +1384,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
+ return;
+ }
/* PLB to OPB bridge */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
@@ -1509,6 +1510,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
+ }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 320c61a7f36c..31139c1554de 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -309,7 +309,9 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ dev = qdev_new(TYPE_PPC405_PLB);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* interrupt controllers */
for (i = 0; i < ARRAY_SIZE(uic); i++) {
--
2.37.1
- Re: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU, (continued)
[PATCH v3 08/22] ppc/ppc4xx: Introduce a DCR device model, Cédric Le Goater, 2022/08/08
[PATCH v3 09/22] ppc/ppc405: QOM'ify CPC, Cédric Le Goater, 2022/08/08
[PATCH v3 11/22] ppc/ppc405: QOM'ify OCM, Cédric Le Goater, 2022/08/08
[PATCH v3 17/22] ppc/ppc405: QOM'ify PLB,
Cédric Le Goater <=
[PATCH v3 10/22] ppc/ppc405: QOM'ify GPT, Cédric Le Goater, 2022/08/08
[PATCH v3 12/22] ppc/ppc405: QOM'ify GPIO, Cédric Le Goater, 2022/08/08
[PATCH v3 18/22] ppc/ppc405: QOM'ify MAL, Cédric Le Goater, 2022/08/08
[PATCH v3 14/22] ppc/ppc405: QOM'ify EBC, Cédric Le Goater, 2022/08/08
[PATCH v3 13/22] ppc/ppc405: QOM'ify DMA, Cédric Le Goater, 2022/08/08
[PATCH v3 15/22] ppc/ppc405: QOM'ify OPBA, Cédric Le Goater, 2022/08/08