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[PULL 37/62] target/ppc: create an interrupt masking method for POWER7
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 37/62] target/ppc: create an interrupt masking method for POWER7 |
Date: |
Fri, 28 Oct 2022 13:39:26 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-20-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/excp_helper.c | 108 +++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9fa75c55c9..d99b76ce22 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1685,6 +1685,112 @@ void ppc_cpu_do_interrupt(CPUState *cs)
}
#if defined(TARGET_PPC64)
+static int p7_next_unmasked_interrupt(CPUPPCState *env)
+{
+ bool async_deliver;
+
+ /* External reset */
+ if (env->pending_interrupts & PPC_INTERRUPT_RESET) {
+ return PPC_INTERRUPT_RESET;
+ }
+ /* Machine check exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
+ return PPC_INTERRUPT_MCK;
+ }
+
+ /*
+ * For interrupts that gate on MSR:EE, we need to do something a
+ * bit more subtle, as we need to let them through even when EE is
+ * clear when coming out of some power management states (in order
+ * for them to become a 0x100).
+ */
+ async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
+
+ /* Hypervisor decrementer exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
+ /* LPCR will be clear when not supported so this will work */
+ bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
+ /* HDEC clears on delivery */
+ return PPC_INTERRUPT_HDECR;
+ }
+ }
+
+ /* Hypervisor virtualization interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
+ /* LPCR will be clear when not supported so this will work */
+ bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
+ return PPC_INTERRUPT_HVIRT;
+ }
+ }
+
+ /* External interrupt can ignore MSR:EE under some circumstances */
+ if (env->pending_interrupts & PPC_INTERRUPT_EXT) {
+ bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ /* HEIC blocks delivery to the hypervisor */
+ if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
+ !FIELD_EX64(env->msr, MSR, PR))) ||
+ (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
+ return PPC_INTERRUPT_EXT;
+ }
+ }
+ if (FIELD_EX64(env->msr, MSR, CE)) {
+ /* External critical interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_CEXT) {
+ return PPC_INTERRUPT_CEXT;
+ }
+ }
+ if (async_deliver != 0) {
+ /* Watchdog timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_WDT) {
+ return PPC_INTERRUPT_WDT;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) {
+ return PPC_INTERRUPT_CDOORBELL;
+ }
+ /* Fixed interval timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_FIT) {
+ return PPC_INTERRUPT_FIT;
+ }
+ /* Programmable interval timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_PIT) {
+ return PPC_INTERRUPT_PIT;
+ }
+ /* Decrementer exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
+ return PPC_INTERRUPT_DECR;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
+ return PPC_INTERRUPT_DOORBELL;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) {
+ return PPC_INTERRUPT_HDOORBELL;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_PERFM) {
+ return PPC_INTERRUPT_PERFM;
+ }
+ /* Thermal interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_THERM) {
+ return PPC_INTERRUPT_THERM;
+ }
+ /* EBB exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_EBB) {
+ /*
+ * EBB exception must be taken in problem state and
+ * with BESCR_GE set.
+ */
+ if (FIELD_EX64(env->msr, MSR, PR) &&
+ (env->spr[SPR_BESCR] & BESCR_GE)) {
+ return PPC_INTERRUPT_EBB;
+ }
+ }
+ }
+
+ return 0;
+}
+
#define P8_UNUSED_INTERRUPTS \
(PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_HVIRT | \
PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \
@@ -1972,6 +2078,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
switch (env->excp_model) {
#if defined(TARGET_PPC64)
+ case POWERPC_EXCP_POWER7:
+ return p7_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER8:
return p8_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER9:
--
2.37.3
- [PULL 27/62] target/ppc: remove generic architecture checks from p9_deliver_interrupt, (continued)
- [PULL 27/62] target/ppc: remove generic architecture checks from p9_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 28/62] target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER9, Daniel Henrique Barboza, 2022/10/28
- [PULL 29/62] target/ppc: add power-saving interrupt masking logic to p9_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 30/62] target/ppc: create an interrupt masking method for POWER8, Daniel Henrique Barboza, 2022/10/28
- [PULL 31/62] target/ppc: remove unused interrupts from p8_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 32/62] target/ppc: create an interrupt deliver method for POWER8, Daniel Henrique Barboza, 2022/10/28
- [PULL 33/62] target/ppc: remove unused interrupts from p8_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 35/62] target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER8, Daniel Henrique Barboza, 2022/10/28
- [PULL 36/62] target/ppc: add power-saving interrupt masking logic to p8_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 34/62] target/ppc: remove generic architecture checks from p8_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 37/62] target/ppc: create an interrupt masking method for POWER7,
Daniel Henrique Barboza <=
- [PULL 38/62] target/ppc: remove unused interrupts from p7_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 40/62] target/ppc: remove unused interrupts from p7_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 41/62] target/ppc: remove generic architecture checks from p7_deliver_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 39/62] target/ppc: create an interrupt deliver method for POWER7, Daniel Henrique Barboza, 2022/10/28
- [PULL 42/62] target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER7, Daniel Henrique Barboza, 2022/10/28
- [PULL 43/62] target/ppc: add power-saving interrupt masking logic to p7_next_unmasked_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 44/62] target/ppc: remove ppc_store_lpcr from CONFIG_USER_ONLY builds, Daniel Henrique Barboza, 2022/10/28
- [PULL 45/62] target/ppc: introduce ppc_maybe_interrupt, Daniel Henrique Barboza, 2022/10/28
- [PULL 46/62] target/ppc: unify cpu->has_work based on cs->interrupt_request, Daniel Henrique Barboza, 2022/10/28
- [PULL 47/62] target/ppc: move the p*_interrupt_powersave methods to excp_helper.c, Daniel Henrique Barboza, 2022/10/28