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[PATCH v2 7/9] target/riscv/cpu: Restrict some sysemu-specific fields fr
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 7/9] target/riscv/cpu: Restrict some sysemu-specific fields from CPUArchState |
Date: |
Sat, 17 Dec 2022 18:29:05 +0100 |
The 'hwaddr' type is only available / meaningful on system emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.h | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 05fafebff7..71ea1bb411 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -370,7 +370,7 @@ struct CPUArchState {
uint64_t menvcfg;
target_ulong senvcfg;
uint64_t henvcfg;
-#endif
+
target_ulong cur_pmmask;
target_ulong cur_pmbase;
@@ -388,6 +388,7 @@ struct CPUArchState {
uint64_t kvm_timer_compare;
uint64_t kvm_timer_state;
uint64_t kvm_timer_frequency;
+#endif
};
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
@@ -553,12 +554,20 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
+#ifndef CONFIG_USER_ONLY
+hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int
mmu_idx,
uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+#endif
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
@@ -566,12 +575,6 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
-hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
--
2.38.1
- [PATCH v2 0/9] target/misc: Header cleanups around "cpu.h", Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 1/9] target/alpha: Remove obsolete STATUS document, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 2/9] target/loongarch/cpu: Remove unused "sysbus.h" header, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 3/9] target/loongarch/cpu: Restrict "memory.h" header to sysemu, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 4/9] target/ppc/internal: Restrict MMU declarations to sysemu, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 5/9] target/ppc/kvm: Remove unused "sysbus.h" header, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 6/9] target/riscv/cpu: Move Floating-Point fields closer, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 7/9] target/riscv/cpu: Restrict some sysemu-specific fields from CPUArchState,
Philippe Mathieu-Daudé <=
- [PATCH v2 8/9] target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard, Philippe Mathieu-Daudé, 2022/12/17
- [PATCH v2 9/9] target/xtensa/cpu: Include missing "memory.h" header, Philippe Mathieu-Daudé, 2022/12/17