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[PULL 04/20] target/mips: Fix SWM32 handling for microMIPS
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 04/20] target/mips: Fix SWM32 handling for microMIPS |
Date: |
Wed, 8 Mar 2023 00:46:55 +0100 |
From: Marcin Nowakowski <marcin.nowakowski@fungible.com>
SWM32 should store a sequence of 32-bit words from the GPRs, but it was
incorrectly coded to store 16-bit words only. As a result, an LWM32 that
usually follows would restore invalid register values.
Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of
MMU_MODE*_SUFFIX")
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230216051717.3911212-3-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index d0bd0267b2..c1a8380e34 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -248,14 +248,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr,
target_ulong reglist,
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
+ cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
mem_idx, GETPC());
addr += 4;
}
}
if (do_r31) {
- cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+ cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
}
}
--
2.38.1
- [PULL 00/20] MIPS patches for 2023-03-07, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 01/20] docs/system: Remove "mips" board from target-mips.rst, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 02/20] target/mips: Replace [g_]assert(0) -> g_assert_not_reached(), Philippe Mathieu-Daudé, 2023/03/07
- [PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 04/20] target/mips: Fix SWM32 handling for microMIPS,
Philippe Mathieu-Daudé <=
- [PULL 05/20] target/mips: Implement CP0.Config7.WII bit support, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c), Philippe Mathieu-Daudé, 2023/03/07
- [PULL 07/20] hw/mips: Declare all length properties as unsigned, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 08/20] hw/mips/itu: Pass SAAR using QOM link property, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 09/20] Revert "hw/isa/i82378: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 10/20] Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 11/20] hw/display/sm501: Add debug property to control pixman usage, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 12/20] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 13/20] hw/isa/vt82c686: Implement PCI IRQ routing, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing, Philippe Mathieu-Daudé, 2023/03/07