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[PULL 03/10] target/ppc: Alignment faults do not set DSISR in ISA v3.0 o
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 03/10] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward |
Date: |
Sun, 28 May 2023 13:49:15 -0300 |
From: Nicholas Piggin <npiggin@gmail.com>
This optional behavior was removed from the ISA in v3.0, see
Summary of Changes preface:
Data Storage Interrupt Status Register for Alignment Interrupt:
Simplifies the Alignment interrupt by remov- ing the Data Storage
Interrupt Status Register (DSISR) from the set of registers modified
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230515092655.171206-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/excp_helper.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 199328f4b6..fea9221501 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1431,13 +1431,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int
excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
- /*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
- */
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ /* Optional DSISR update was removed from ISA v3.0 */
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ }
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
--
2.40.1
- [PULL 00/10] ppc queue, Daniel Henrique Barboza, 2023/05/28
- [PULL 01/10] target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs, Daniel Henrique Barboza, 2023/05/28
- [PULL 02/10] target/ppc: Fix width of some 32-bit SPRs, Daniel Henrique Barboza, 2023/05/28
- [PULL 03/10] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward,
Daniel Henrique Barboza <=
- [PULL 04/10] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall, Daniel Henrique Barboza, 2023/05/28
- [PULL 05/10] hw/ppc/prep: Fix wiring of PIC -> CPU interrupt, Daniel Henrique Barboza, 2023/05/28
- [PULL 07/10] pnv_lpc: disable reentrancy detection for lpc-hc, Daniel Henrique Barboza, 2023/05/28
- [PULL 06/10] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs, Daniel Henrique Barboza, 2023/05/28
- [PULL 08/10] target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRF, Daniel Henrique Barboza, 2023/05/28
- [PULL 09/10] target/ppc: Add POWER9 DD2.2 model, Daniel Henrique Barboza, 2023/05/28
- [PULL 10/10] ppc/pegasos2: Change default CPU to 7457, Daniel Henrique Barboza, 2023/05/28
- Re: [PULL 00/10] ppc queue, Michael Tokarev, 2023/05/28