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[PULL 40/75] target/ppc: Move powerpc_mmu_t definition to 'cpu.h'
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 40/75] target/ppc: Move powerpc_mmu_t definition to 'cpu.h' |
Date: |
Tue, 7 Nov 2023 13:24:30 +0100 |
The powerpc_mmu_t definition is only used by target/ppc/, no need
to expose it. Restrict it by moving it to "target/ppc/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20231013125630.95116-7-philmd@linaro.org>
---
target/ppc/cpu-qom.h | 43 -------------------------------------------
target/ppc/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index acc5f1a1dc..c35374e15f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -35,49 +35,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass,
POWERPC_CPU)
#define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
-/*****************************************************************************/
-/* MMU model */
-typedef enum powerpc_mmu_t powerpc_mmu_t;
-enum powerpc_mmu_t {
- POWERPC_MMU_UNKNOWN = 0x00000000,
- /* Standard 32 bits PowerPC MMU */
- POWERPC_MMU_32B = 0x00000001,
- /* PowerPC 6xx MMU with software TLB */
- POWERPC_MMU_SOFT_6xx = 0x00000002,
- /*
- * PowerPC 74xx MMU with software TLB (this has been
- * disabled, see git history for more information.
- * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
- */
- POWERPC_MMU_SOFT_74xx = 0x00000003,
- /* PowerPC 4xx MMU with software TLB */
- POWERPC_MMU_SOFT_4xx = 0x00000004,
- /* PowerPC MMU in real mode only */
- POWERPC_MMU_REAL = 0x00000006,
- /* Freescale MPC8xx MMU model */
- POWERPC_MMU_MPC8xx = 0x00000007,
- /* BookE MMU model */
- POWERPC_MMU_BOOKE = 0x00000008,
- /* BookE 2.06 MMU model */
- POWERPC_MMU_BOOKE206 = 0x00000009,
-#define POWERPC_MMU_64 0x00010000
- /* 64 bits PowerPC MMU */
- POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
- /* Architecture 2.03 and later (has LPCR) */
- POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
- /* Architecture 2.06 variant */
- POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
- /* Architecture 2.07 variant */
- POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
- /* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
-};
-
-static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
-{
- return mmu_model & POWERPC_MMU_64;
-}
-
/*****************************************************************************/
/* Input pins model */
typedef enum powerpc_input_t powerpc_input_t;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 94a804a605..d859c45a2e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -219,6 +219,48 @@ typedef enum powerpc_excp_t {
POWERPC_EXCP_POWER10,
} powerpc_excp_t;
+/*****************************************************************************/
+/* MMU model */
+typedef enum powerpc_mmu_t {
+ POWERPC_MMU_UNKNOWN = 0x00000000,
+ /* Standard 32 bits PowerPC MMU */
+ POWERPC_MMU_32B = 0x00000001,
+ /* PowerPC 6xx MMU with software TLB */
+ POWERPC_MMU_SOFT_6xx = 0x00000002,
+ /*
+ * PowerPC 74xx MMU with software TLB (this has been
+ * disabled, see git history for more information.
+ * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
+ */
+ POWERPC_MMU_SOFT_74xx = 0x00000003,
+ /* PowerPC 4xx MMU with software TLB */
+ POWERPC_MMU_SOFT_4xx = 0x00000004,
+ /* PowerPC MMU in real mode only */
+ POWERPC_MMU_REAL = 0x00000006,
+ /* Freescale MPC8xx MMU model */
+ POWERPC_MMU_MPC8xx = 0x00000007,
+ /* BookE MMU model */
+ POWERPC_MMU_BOOKE = 0x00000008,
+ /* BookE 2.06 MMU model */
+ POWERPC_MMU_BOOKE206 = 0x00000009,
+#define POWERPC_MMU_64 0x00010000
+ /* 64 bits PowerPC MMU */
+ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
+ /* Architecture 2.03 and later (has LPCR) */
+ POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
+ /* Architecture 2.06 variant */
+ POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
+ /* Architecture 2.07 variant */
+ POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
+ /* Architecture 3.00 variant */
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
+} powerpc_mmu_t;
+
+static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
+{
+ return mmu_model & POWERPC_MMU_64;
+}
+
#define PPC_INPUT(env) ((env)->bus_model)
/*****************************************************************************/
--
2.41.0
- [PULL 00/75] Misc HW/UI patches for 2023-11-07, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 36/75] target/ppc: Define powerpc_pm_insn_t in 'internal.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 37/75] target/ppc: Move ppc_cpu_class_by_name() declaration to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 38/75] target/ppc: Move PowerPCCPUClass definition to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 39/75] target/ppc: Move powerpc_excp_t definition to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 40/75] target/ppc: Move powerpc_mmu_t definition to 'cpu.h',
Philippe Mathieu-Daudé <=
- [PULL 43/75] hw/s390x/sclp: Have sclp_service_call[_protected]() take S390CPU*, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 42/75] hw/s390x/css: Have css_do_sic() take S390CPU instead of CPUS390XState, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 41/75] target/ppc: Move powerpc_input_t definition to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 45/75] target/s390x/cpu: Restrict CPUS390XState declaration to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 44/75] target/s390x/cpu: Restrict cpu_get_tb_cpu_state() definition to TCG, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 68/75] hw/sd: Declare QOM types using DEFINE_TYPES() macro, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 72/75] MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 47/75] target: Move ArchCPUClass definition to 'cpu.h', Philippe Mathieu-Daudé, 2023/11/07
- [PULL 51/75] hw/cpu: Clean up global variable shadowing, Philippe Mathieu-Daudé, 2023/11/07
- [PULL 73/75] MAINTAINERS: Add more guest-agent related files to the corresponding section, Philippe Mathieu-Daudé, 2023/11/07