Re: [PATCH 0/7] ppc: pnv ChipTOD and various timebase fixes

[Nicholas Piggin]

On Fri Nov 24, 2023 at 3:09 AM AEST, Cédric Le Goater wrote:
> On 11/23/23 11:30, Nicholas Piggin wrote:
> > The chiptod/TFMR/state machine is not really tied to the other
> > time register fixes, but they touch some of the same code, and
> > logically same facility.
> > 
> > Changes since v1 of chiptod patches:
> > - Split hackish ChipTOD<->TFMR/TBST interface into its own patch
> > - Fix multi-socket addressing on P9 / chip ID mode (P10 works)
> > - Change chiptod primary/secondary setting to use class properties
> > - Add more comments to explain TOD overview and timebase state
> >    machine.
> > - SMT support for TFMR, some functionality is limited to thread 0.
> > - FIRMWARE_CONTROL_ERROR bit implemented in TFMR.
> > - Misc cleanups and bug fixes.
> > 
> > The hacky part, addressing core from chiptod, is still hacky. Is
> > there strong objection to it?
>
> Dunno yet :)

Thanks for the nice review!

> > This successfully runs skiboot chiptod initialisation code with
> > POWER9 and POWER10 multi-socket, multi-core, SMT. That requires
> > skiboot 7.1 (not in-tree), otherwise chiptod init is skipped on
> > QEMU machines.
>
> Let's update skiboot at the same time then.

Yeah, I'll update skiboot ahead of adding merging this.

Thanks,
Nick