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[PATCH 07/26] target/ppc: Improve timebase register defines naming
From: |
Nicholas Piggin |
Subject: |
[PATCH 07/26] target/ppc: Improve timebase register defines naming |
Date: |
Fri, 19 Jan 2024 01:06:25 +1000 |
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.
The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 8 ++++----
target/ppc/helper_regs.c | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f8101ffa29..848e583c2d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1750,8 +1750,8 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_USPRG5 (0x105)
#define SPR_USPRG6 (0x106)
#define SPR_USPRG7 (0x107)
-#define SPR_VTBL (0x10C)
-#define SPR_VTBU (0x10D)
+#define SPR_TBL (0x10C)
+#define SPR_TBU (0x10D)
#define SPR_SPRG0 (0x110)
#define SPR_SPRG1 (0x111)
#define SPR_SPRG2 (0x112)
@@ -1764,8 +1764,8 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_SPRG7 (0x117)
#define SPR_ASR (0x118)
#define SPR_EAR (0x11A)
-#define SPR_TBL (0x11C)
-#define SPR_TBU (0x11D)
+#define SPR_WR_TBL (0x11C)
+#define SPR_WR_TBU (0x11D)
#define SPR_TBU40 (0x11E)
#define SPR_SVR (0x11E)
#define SPR_BOOKE_PIR (0x11E)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 7d8e041fb3..ead4acede4 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -466,22 +466,22 @@ void register_generic_sprs(PowerPCCPU *cpu)
/* Time base */
#if defined(TARGET_PPC64)
- spr_register(env, SPR_VTBL, "TB",
+ spr_register(env, SPR_TBL, "TB",
#else
- spr_register(env, SPR_VTBL, "TBL",
+ spr_register(env, SPR_TBL, "TBL",
#endif
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_TBL, "TBL",
+ spr_register(env, SPR_WR_TBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, &spr_write_tbl,
0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
+ spr_register(env, SPR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_TBU, "TBU",
+ spr_register(env, SPR_WR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, &spr_write_tbu,
0x00000000);
--
2.42.0
- [PATCH 00/26] target/ppc: TCG improvements and fixes, Nicholas Piggin, 2024/01/18
- [PATCH 01/26] target/ppc: Fix crash on machine check caused by ifetch, Nicholas Piggin, 2024/01/18
- [PATCH 02/26] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/01/18
- [PATCH 03/26] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/01/18
- [PATCH 04/26] target/ppc: Rename registers to match ISA, Nicholas Piggin, 2024/01/18
- [PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/01/18
- [PATCH 06/26] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/01/18
- [PATCH 07/26] target/ppc: Improve timebase register defines naming,
Nicholas Piggin <=
- [PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions, Nicholas Piggin, 2024/01/18
- [PATCH 09/26] pnv/chiptod: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/01/18
- [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/01/18
- [PATCH 11/26] pnv/chiptod: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/01/18
- [PATCH 12/26] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/01/18
- [PATCH 13/26] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/01/18
- [PATCH 14/26] target/ppc: Add new hflags to support BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 15/26] target/ppc: Add recording of taken branches to BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 17/26] target/ppc: Add migration support for BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 18/26] target/ppc: BookE DECAR SPR is 32-bit, Nicholas Piggin, 2024/01/18