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From: | BALATON Zoltan |
Subject: | Re: [PATCH 1/6] target/ppc: Fix 440 tlbwe TLB invalidation gaps |
Date: | Fri, 16 Feb 2024 14:28:36 +0100 (CET) |
On Thu, 18 Jan 2024, Nicholas Piggin wrote:
The 440 software TLB write entry misses several cases that must flush the TCG TLB: - If the new size is smaller than the existing size, the EA no longer covered should be flushed. This looks like an inverted inequality test. - If the TLB PID changes. - If the TLB attr bit 0 (translation address space) changes. - If low prot (access control) bits change. Fix this by removing tricks to avoid TLB flushes, and just invalidate the TLB if any valid entry is being changed, similarly to 4xx. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This series was missing a cover letter so patchew did not pick it up correctly. However this improves the sam460ex performance a lot so I'd like this to be included in 9.0 release. Nick, maybe it's time to start merging patches and send a pull request to avoid getting conflicts in last minute that could cause series to miss release. So an early pull request would help to get everybody on the same page.
Regards, BALATON Zoltan
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