Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen

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Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_ar

From:	Bastian Koppelmann
Subject:	Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
Date:	Mon, 21 Jan 2019 10:07:40 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0


On 1/20/19 2:24 AM, Richard Henderson wrote:

On 1/19/19 12:14 AM, Bastian Koppelmann wrote:

  static bool trans_slli(DisasContext *ctx, arg_slli *a)
  {
-    gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+    if (a->rd != 0) {
+        TCGv t = tcg_temp_new();
+        gen_get_gpr(t, a->rs1);
+
+        if (a->shamt >= TARGET_LONG_BITS) {
+            return false;
+        }

I think the shmat test should be first, so that

        slli    r0, r1, 99

produces SIGILL instead of translating to a nop.



Oh, that is a very good catch. Thanks.


Cheers,

Bastian

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[Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), (continued)
- [Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/18
  - Re: [Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Richard Henderson, 2019/01/19
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/21
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Richard Henderson, 2019/01/21
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/18
  - Re: [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Richard Henderson, 2019/01/19
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/18
  - Re: [Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Richard Henderson, 2019/01/19
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/21
- [Qemu-riscv] [PATCH v4 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/18

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