[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV3
|
From: |
Alistair Francis |
|
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree |
|
Date: |
Tue, 22 Jan 2019 16:08:57 -0800 |
On Tue, Jan 22, 2019 at 1:57 AM Bastian Koppelmann
<address@hidden> wrote:
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/insn32.decode | 28 +++
> target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 3 files changed, 344 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e40836bf03..e64b2b5e34 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
> fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
> fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
> +
> +# *** RV32D Standard Extension ***
> +fld ............ ..... 011 ..... 0000111 @i
> +fsd ....... ..... ..... 011 ..... 0100111 @s
> +fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
> +fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
> +fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
> +fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
> +fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
> +fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
> +fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
> +fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
> +fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
> +fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
> +fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
> +fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
> +fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
> +fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
> +fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
> +feq_d 1010001 ..... ..... 010 ..... 1010011 @r
> +flt_d 1010001 ..... ..... 001 ..... 1010011 @r
> +fle_d 1010001 ..... ..... 000 ..... 1010011 @r
> +fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
> +fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
> +fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
> diff --git a/target/riscv/insn_trans/trans_rvd.inc.c
> b/target/riscv/insn_trans/trans_rvd.inc.c
> new file mode 100644
> index 0000000000..a7e2335ffa
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvd.inc.c
> @@ -0,0 +1,315 @@
> +/*
> + * RISC-V translation routines for the RV64D Standard Extension.
> + *
> + * Copyright (c) 2016-2017 Sagar Karandikar, address@hidden
> + * Copyright (c) 2018 Peer Adelt, address@hidden
> + * Bastian Koppelmann, address@hidden
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_fld(DisasContext *ctx, arg_fld *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> +{
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> + REQUIRE_FPU;
> + tcg_gen_addi_tl(t0, t0, a->imm);
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
> +
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
> +{
> + REQUIRE_FPU;
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
> + cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
> + return true;
> +}
> +
> +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
> +{
> + if (a->rs1 == a->rs2) { /* FMOV */
> + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
> + } else {
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
> + cpu_fpr[a->rs1], 0, 63);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FNEG */
> + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
> + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
> +{
> + REQUIRE_FPU;
> + if (a->rs1 == a->rs2) { /* FABS */
> + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
> + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
> + tcg_temp_free_i64(t0);
> + }
> + return true;
> +}
> +
> +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
> + cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
> +{
> + REQUIRE_FPU;
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
> +
> + return true;
> +}
> +
> +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> + return true;
> +}
> +
> +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> + gen_set_gpr(a->rd, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> +
> +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
> +{
> + REQUIRE_FPU;
> +
> + TCGv t0 = tcg_temp_new();
> + gen_get_gpr(t0, a->rs1);
> +
> + gen_set_rm(ctx, a->rm);
> + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
> + tcg_temp_free(t0);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 933ca9fb69..7f3443db20 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
> #include "insn_trans/trans_rvm.inc.c"
> #include "insn_trans/trans_rva.inc.c"
> #include "insn_trans/trans_rvf.inc.c"
> +#include "insn_trans/trans_rvd.inc.c"
>
> static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> {
> --
> 2.20.1
>
>
- [Qemu-riscv] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree,
Alistair Francis <=
- [Qemu-riscv] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/01/22