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[Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is correctly cast |
Date: |
Sat, 9 Feb 2019 00:59:29 +0000 |
Cast the kernel start address to the target bit length.
This ensures that we calculate the initrd offset to a valid address for
the architecture.
Steps to reproduce the original problem (reported by Alex):
Build U-Boot for the virt machine for riscv32. Then run it with
$ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file>
You can find the initrd address with
U-Boot# fdt addr $fdtcontroladdr
U-Boot# fdt ls /chosen
Then take a peek at that address:
U-Boot# md.b <addr>
and you will see that there is nothing there without this patch. The
reason is that the binary was loaded to a negative address.
Signed-off-by: Alistair Francis <address@hidden>
Suggested-by: Alexander Graf <address@hidden>
Reported-by: Alexander Graf <address@hidden>
---
v3:
- Add steps to reproduce
v2:
- Remove old comment
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index bfc086609c..b1cd11363c 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -74,7 +74,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2730b25b60..7bc25820fe 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -65,7 +65,7 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index c66ffc50cc..2a000a5800 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3e8b19c668..fc4c6b306e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,7 +62,7 @@ static const struct MemmapEntry {
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
--
2.20.1
- [Qemu-riscv] [PATCH v1 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is correctly cast,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 02/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 03/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 04/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 05/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 06/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 07/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 09/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 10/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 11/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/08