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[Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decod
From: |
Bastian Koppelmann |
Subject: |
[Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree |
Date: |
Fri, 22 Feb 2019 15:10:02 +0100 |
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
v7 -> v8:
- add missing RVF checks
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60 +++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 0bee95c984..6319f872ac 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 0f83790349..172dbfa919 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -377,3 +377,63 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
return true;
}
+
+#ifdef TARGET_RISCV64
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ tcg_temp_free(t0);
+ return true;
+}
+#endif
--
2.20.1
- [Qemu-riscv] [PATCH v8 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v8 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 19/34] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 06/34] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree,
Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/02/22