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Re: [Qemu-trivial] [PATCH] Possible wrong microMIPS opcode encoding
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-trivial] [PATCH] Possible wrong microMIPS opcode encoding |
Date: |
Wed, 14 Nov 2012 17:45:21 +0100 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Wed, Nov 14, 2012 at 10:49:55AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> Hi all,
>
> While reading microMIPS decoding, I found a possible wrong opcode
> encoding. According to [1] page 337, the bits 13..12 for MULTU is
> 0x01 rather than 0x00. Please review, thanks.
>
> [1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
> Application-Specific Extension to the microMIPS32 Architecture
This is indeed correct, but I guess the page you meant is 166. Page 337
refers to the original MULTU instruction from the MIPS Architecture for
Programmers Volume II-B: The microMIPS32 Instruction Set.
On the other the microMIPS32 encoding for DSP instruction is not yet
supported.
> Signed-off-by: Chen Wei-Ren <address@hidden>
> ---
> target-mips/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index f6fc0c2..01b48fa 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10385,7 +10385,7 @@ enum {
>
> /* bits 13..12 for 0x32 */
> MULT_ACC = 0x0,
> - MULTU_ACC = 0x0,
> + MULTU_ACC = 0x1,
>
> /* bits 15..12 for 0x2c */
> SEB = 0x2,
> --
> 1.7.12.3
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net