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[PULL 13/17] docs/cxl: Change to lowercase as others
From: |
Michael Tokarev |
Subject: |
[PULL 13/17] docs/cxl: Change to lowercase as others |
Date: |
Thu, 21 Sep 2023 11:35:02 +0300 |
From: Li Zhijian <lizhijian@cn.fujitsu.com>
Using the same style as elsewhere for topology / topo
Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
Link:
https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---
docs/system/devices/cxl.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f12011e230..b742120657 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within
the CFMWs
and exposing those via normal memory configurations as would be done
for system RAM.
-Example system Topology. x marks the match in each decoder level::
+Example system topology. x marks the match in each decoder level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
@@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder
level::
___________|___ __________|__ __|_________ ___|_________
(3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
| Appears in | | Appears in | | Appears in | | Appear in |
- | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
- | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
+ | PCI topology | | PCI topology| | PCI topo | | PCI topo |
+ | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
|_______________| |_____________| |____________| |_____________|
| | | |
| | | |
@@ -272,7 +272,7 @@ Example topology involving a switch::
| Root Port 0 |
| Appears in |
| PCI topology |
- | As 0c:00.0 |
+ | as 0c:00.0 |
|___________x___|
|
|
--
2.39.2
- [PULL 05/17] hw/pci: spelling fixes, (continued)
- [PULL 05/17] hw/pci: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 01/17] ppc: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 09/17] hw/i386/pc: fix code comment on cumulative flash size, Michael Tokarev, 2023/09/21
- [PULL 02/17] bsd-user: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 04/17] hw/net: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 11/17] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS, Michael Tokarev, 2023/09/21
- [PULL 08/17] subprojects: Use the correct .git suffix in the repository URLs, Michael Tokarev, 2023/09/21
- [PULL 06/17] hw/tpm: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 07/17] hw/other: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 10/17] hw/cxl: Fix CFMW config memory leak, Michael Tokarev, 2023/09/21
- [PULL 13/17] docs/cxl: Change to lowercase as others,
Michael Tokarev <=
- [PULL 12/17] hw/cxl/cxl_device: Replace magic number in CXLError definition, Michael Tokarev, 2023/09/21
- [PULL 14/17] hw/cxl: Fix out of bound array access, Michael Tokarev, 2023/09/21
- [PULL 16/17] docs/cxl: Cleanout some more aarch64 examples., Michael Tokarev, 2023/09/21
- [PULL 15/17] hw/mem/cxl_type3: Add missing copyright and license notice, Michael Tokarev, 2023/09/21
- [PULL 17/17] docs/devel/reset.rst: Correct function names, Michael Tokarev, 2023/09/21
- Re: [PULL 00/17] Trivial patches for 2023-09-21, Stefan Hajnoczi, 2023/09/21