[avr-libc-dev] wdt.h watchdog code - will an interrupt mess up the timing ?

[Jeff Kowing]

First, thanks to all avr-libc developers for this great library!
Second, I was wondering if anyone could help answer some confusion I
have about how the watchdog routines are implemented.  


The inline asm code in wdt.h for _wdt_write(value) is approximately:

1. in __tmp_reg__, __SREG__
2. cli
3. wdr
4. out _WD_CONTROL_REG, _BV(_WD_CHANGE_BIT) | _BV(WDE)
5. out __SREG__, __tmp_reg__
6. out _WD_CONTROL_REG, _BV(WDE) | (value & 0x7)

I understand that line 6 must execute within 4 cycles after line 4 for
the watchdog to be enabled and its timeout period to be properly set (at
least for an ATMega128 with safety level 1 fuse setting).

My concern is that since global interrupts are potentially re-enabled on
line 5, what prevents an interrupt routine from triggering before line 6
gets executed ?  I believe that the instruction following a "sei"
instruction is guaranteed to execute before any pending interrupts are
handled, but is the same true when using an "in" instruction to set the
I bit ?

My other question concerns wdt_disable():

1. in __tmp_reg__, __SREG__
2. out _WD_CONTROL_REG, _BV(_WD_CHANGE_BIT) | _BV(WDE)
3. out _WD_CONTROL_REG, __zero_reg__
4. out __SREG__, __tmp_reg__

This one really confuses me because there is no "cli", so what prevents
an interrupt routine from messing up the critical timing between line 2
and line 3 ?  And why is __SREG__ being saved and restored without a
cli ? Maybe this is a bug or more likely I just have a lot more to
learn !

Regards,
Jeff

-- 
Jeff Kowing <address@hidden>
Opinions expressed are my own and not necessarily those of my employer.