On ARM FIQ banked registers are case sensitive.

[address@hidden]

Hi,

I'm developing software using ARM Virtualization Extension. I use some
macros to shorten up some code, but my issue generally just narrows to
assembler, it seems.

I'm using msr/mrs instructions and while:

mrs SP_SVC, r1

works, the:

mrs SP_FIQ, r1

gives:

/tmp/ccZWskys.s:490: Error: selected processor does not support
requested special purpose register -- `msr SP_FIQ,r1'

only after I change to:

mrs SP_fiq, r1

the problem is gone.

This is not a big deal, but I still need a workaround for this in my
code. That's why I would like to report it. I guess register names
should be case insensitive.

I tried a lot of toolchains (different versions from linaro and
codesourcery) and all seem to be affected.

Regards,
--
Dawid Ciężarkiewicz