[Bug binutils/26259] New: Can't generate ORR instruction

[Alexei.Fedorov at arm dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=26259

            Bug ID: 26259
           Summary: Can't generate ORR instruction
           Product: binutils
           Version: unspecified
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: binutils
          Assignee: unassigned at sourceware dot org
          Reporter: Alexei.Fedorov at arm dot com
  Target Milestone: ---

Hello.
I have a problem with ORR instruction in GCC 11.0.0 assembler.
orr w28,w28,#0x800080
is compiled with 0x3209839C encoding:

EL2N:0x0000000088013CA8 : ORR      w28,w28,#0x800080

orr x28,x28,#0x800080
generates
Error: immediate out of range at operand 3 -- `orr x28,x28,#0x800080'
If I modify encoding 0x3209839C for W28 in debugger
by setting 'sf' bit 31, according to ARM ARM:
"64-bit variant
Applies when sf == 1.
ORR <Xd|SP>, <Xn>, #<imm>"

Disassembly shows 
EL2N:0x0000000088013CA8 : ORR      x28,x28,#0x80008000800080
but when I execute it with initial X28 = 0, the result is
X28     0x0000000000800080

which is correct. Any ideas what might be wrong here?

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