[Bug ld/28410] Prevent region check failures when relaxation is not final

[nelsonc1225 at sourceware dot org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28410

--- Comment #2 from Nelson Chu <nelsonc1225 at sourceware dot org> ---
commit abd20cb637008da9d32018b4b03973e119388a0a
Refs: users/ARM/embedded-gdb-master-2018q4-7811-gabd20cb
Author:     Nelson Chu <nelson.chu@sifive.com>
AuthorDate: Tue Nov 17 19:39:52 2020 -0800
Commit:     Nelson Chu <nelson.chu@sifive.com>
CommitDate: Sat Nov 21 09:41:58 2020 +0800

    RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous.

commit ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4
Refs: users/ARM/embedded-gdb-master-2018q4-9197-gebdcad3
Author:     Nelson Chu <nelson.chu@sifive.com>
AuthorDate: Fri Dec 18 10:59:41 2020 +0800
Commit:     Nelson Chu <nelson.chu@sifive.com>
CommitDate: Thu Mar 11 17:27:13 2021 +0800

    RISC-V: Improve multiple relax passes problem.


The commit ebdcad causes troubles for the above testcase.  It is used to
increase the relax chances of the pcrel relaxations, since I separate them to
the different relax pass in commit abd20c, to resolve the dangerous relocation
problem.

However, Lewis Revill's solution should work well, but the changes of the
generic code (lang_relax_sections) is beyond my expectation.  For now we may
have three options,

1. Keep the commit ebdcad, and use Lewis Revill's solution to resolve the
checking region problem.

2. Rewrite the commit ebdcad, don't use an extra target `restart_relax', just
find a way to enhance the `again' and lang_relax_sections can rerun the whole
relaxations.

3. Revert the commit ebdcad in the short-term, since maybe not so many pcgp
relaxations will be affected.  For long-term, we should rewrite the commit
abd20c.  Perhaps we shouldn't separate the pcgp relaxations to the different
relax pass, we should find a way to update the pcgp_relocs table once we
actually delete the code.

My personal opinion is the third option since I really don’t want to change the
generic code only for riscv target.

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