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MEMORY_BARRIERs on P6, Pentium 4 and Xeon

From: Oliver Trachsel
Subject: MEMORY_BARRIERs on P6, Pentium 4 and Xeon
Date: 07 Apr 2003 11:49:17 +0200


The linuxthread package does not seem to use hardware memory barriers on
any IA32 platform. (i.e. {READ|WRITE}MEMORY_BARRIER() use default
definitions from internals.h).

Shouldn't hardware barriers (mfence, sfence and lfence instructions or
locked instructions where the latter are not available) be used on
Pentium 4, Intel Xeon and P6 Family processors?

According to the Intel Architecture Software Developer's Manual (Volume
3, Sections 7.2.1 and 7.2.2) these processor's memory model is weaker
than those of i486 and Pentium CPUs and fences should be used to ensure
correct ordering of memory accesses.


Oliver Trachsel
Laboratory for Software Technology
ETH Zurich, Switzerland

Phone: +41 1 63 27334
Email: oliver.trachsel at inf.ethz.ch

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