Re: [Bug-gnucap] error with current-mirror

[Al Davis]

On Saturday 17 January 2004 07:55 am, Michael De Nil wrote:
> While simulating some current-mirror circuits, I got stuck on some
> weird error... I don't know if this is a bug, non-implemented or just
> some stupid mistake of myselve ;)

It is a classic transient analysis convergence failure.  The equivalent 
message in Spice is "internal timestep too small".

The DC solution failed, too, but it kept going anyway.

There is a bug.  Thanks for sending me a test case that demonstrates it.  
The bug is in the node limiting heuristics.  There is a trap for wild 
voltages, which usually helps convergence, that is tuned based on the 
values of fixed voltage sources. 

The cuplprit is this one:
  Vee     0       99      10
If you reverse it, so it reads:
  Vee     99     0        -10
it works correctly.
There should be no difference, but there is.  I fixed it, so the next 
development release will have the fix.



To give you some more detail, here is an explanation of what happens 
when there are convergence problems, which should give an idea of how 
to interpret the messages.

Often the initial DC solution is OK.  It isn't but the simulator decides 
to move on anyway.

Then it steps forward in time.  It works fine for a while then 
convergence fails.

It tries to correct for it by rejecting the most recent solution, and 
trying again at a smaller time step.

Maybe this works, maybe it doesn't.  Most likely it will go a step or 
two at the smaller step, then fail again.  Repeat the process.

Eventually, this goes too far, and time starts moving backwards.  OK, 
once.  But it still fails, and tries to move backwards again...

> did not converge
>  0.        -0.071605

Initial DC solution didn't converge either, but it gave you an answer 
anyway.  It is probably wrong.  Spice would have stopped here.

> very backward time step

It is trying to go backwards in time, too far.  Gnucap can bo backwards 
a little bit, but it went back beyond the stored history.

> convergence failure (itl4)

The number of iterations exceeded the option "ITL4".

> zero time step

Step control algorithm bug.  It tries to recover.

> internal error: step control (adt=1e-12,rdt=-6.10352e-13)

It attempts recovery by forcing an Actual DT of 1e-12, even though the 
requsted DT is -6.1..e-13 (backwards).

> time0=2.2207e-12  time1=1.2207e-12  rtime=6.10352e-13

The error occured at time 2.2207e-12.  The previous step was 1.2207e-12.  
It thinks the next time should be 6.10352e-13.