Use of $* in computed dependencies

[Herb W. Swan]

This is not a bug, but a neat feature that would open the door
to improved functionality, as far as I can see.

The following makefile doesn't do what I had hoped it would:

all:    b.logvsh

b_depend := a.raw.mod

%.logvsh:       $($*_depend) %.mod
        @echo   make $@

%.raw.mod:
        @echo   make $@

%.mod:
        @echo   make $@


Here the first target b.logvsh matches the %.logvsh rule.  It makes
implied target b.mod, and finally it makes b.logvsh.  The printout is:

% make -r
make b.mod
make b.logvsh

Unfortunately, I wanted b.logvsh to also depend on a.raw.mod.  What I
wanted to say is that, in general, %.logvsh targets depend only on their
corresponding %.mod target, but if % happens to be "b", then also make
b.logvsh dependent on b.raw.mod.  I don't know of any other way to do
this except through recursive calls to make, which I'm trying to avoid.

I tried using $(%_depend) instead of $($*_depend), but that didn't work,
either.  I am using

GNU Make version 3.79.1, by Richard Stallman and Roland McGrath.
Built for sparc-sun-solaris2.7
Copyright (C) 1988, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
        Free Software Foundation, Inc.

Is this feature worth considering for a future release?

--



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 | Herbert Swan          | Geoscience Operations             |
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