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[Commit-gnuradio] r3795 - usrp-hw/trunk/sym/generated
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From: |
matt |
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Subject: |
[Commit-gnuradio] r3795 - usrp-hw/trunk/sym/generated |
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Date: |
Sun, 15 Oct 2006 21:54:40 -0600 (MDT) |
Author: matt
Date: 2006-10-15 21:54:40 -0600 (Sun, 15 Oct 2006)
New Revision: 3795
Added:
usrp-hw/trunk/sym/generated/fg320_table.csv
usrp-hw/trunk/sym/generated/xc3sXX00fg320-CFG.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-CLK.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO0.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO1.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO2.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO3.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO4.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO5.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO6.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO7.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-JTAG.src
usrp-hw/trunk/sym/generated/xc3sXX00fg320-PWR.src
usrp-hw/trunk/sym/generated/xilinxgen320
usrp-hw/trunk/sym/generated/xilinxgen456
Removed:
usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src
usrp-hw/trunk/sym/generated/xilinxgen
Modified:
usrp-hw/trunk/sym/generated/Makefile
usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src
usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src
Log:
moved stuff around in the xilinx parts, add 320 pin version
Modified: usrp-hw/trunk/sym/generated/Makefile
===================================================================
--- usrp-hw/trunk/sym/generated/Makefile 2006-10-16 02:54:58 UTC (rev
3794)
+++ usrp-hw/trunk/sym/generated/Makefile 2006-10-16 03:54:40 UTC (rev
3795)
@@ -1,6 +1,6 @@
#!/usr/bin/make
-TRAGESYM=/usr/bin/tragesym
+TRAGESYM=tragesym
SOURCES=ad813x.sym \
ad8347-BIAS.sym \
@@ -124,7 +124,18 @@
xc3sXX00fg456-CLK.sym \
xc3sXX00fg456-PWR.sym \
xc3sXX00fg456-JTAG.sym \
- xc3sXX00fg456-VREF.sym \
+ xc3sXX00fg320-IO0.sym \
+ xc3sXX00fg320-IO1.sym \
+ xc3sXX00fg320-IO2.sym \
+ xc3sXX00fg320-IO3.sym \
+ xc3sXX00fg320-IO4.sym \
+ xc3sXX00fg320-IO5.sym \
+ xc3sXX00fg320-IO6.sym \
+ xc3sXX00fg320-IO7.sym \
+ xc3sXX00fg320-CFG.sym \
+ xc3sXX00fg320-CLK.sym \
+ xc3sXX00fg320-PWR.sym \
+ xc3sXX00fg320-JTAG.sym \
dp83865-CFGLED.sym \
dp83865-CLK.sym \
dp83865-JTAG.sym \
Added: usrp-hw/trunk/sym/generated/fg320_table.csv
===================================================================
--- usrp-hw/trunk/sym/generated/fg320_table.csv (rev 0)
+++ usrp-hw/trunk/sym/generated/fg320_table.csv 2006-10-16 03:54:40 UTC (rev
3795)
@@ -0,0 +1,321 @@
+SORT_ROW,SORT_COLUMN,PIN_NUMBER,XC3S400,XC3S400_TYPE,XC3S1000,XC3S1000_TYPE,XC3S1500,XC3S1500_TYPE,BANK
+A,1,A1,GND,GND,GND,GND,GND,GND,N/A
+A,2,A2,IO_L01N_0/VRP_0,DCI,IO_L01N_0/VRP_0,DCI,IO_L01N_0/VRP_0,DCI,0
+A,3,A3,IO_L01P_0/VRN_0,DCI,IO_L01P_0/VRN_0,DCI,IO_L01P_0/VRN_0,DCI,0
+A,4,A4,IO_L15N_0,I/O,IO_L15N_0,I/O,IO_L15N_0,I/O,0
+A,5,A5,IO_L15P_0,I/O,IO_L15P_0,I/O,IO_L15P_0,I/O,0
+A,6,A6,GND,GND,GND,GND,GND,GND,N/A
+A,7,A7,IO_L30N_0,I/O,IO_L30N_0,I/O,IO_L30N_0,I/O,0
+A,8,A8,IO_L30P_0,I/O,IO_L30P_0,I/O,IO_L30P_0,I/O,0
+A,9,A9,IO_L31P_0/VREF_0,VREF,IO_L31P_0/VREF_0,VREF,IO_L31P_0/VREF_0,VREF,0
+A,10,A10,IO_L31N_1/VREF_1,VREF,IO_L31N_1/VREF_1,VREF,IO_L31N_1/VREF_1,VREF,1
+A,11,A11,IO,I/O,IO,I/O,IO,I/O,1
+A,12,A12,IO/VREF_1,VREF,IO/VREF_1,VREF,IO/VREF_1,VREF,1
+A,13,A13,GND,GND,GND,GND,GND,GND,N/A
+A,14,A14,IO_L16N_1,I/O,IO_L16N_1,I/O,IO_L16N_1,I/O,1
+A,15,A15,IO_L10N_1/VREF_1,VREF,IO_L10N_1/VREF_1,VREF,IO_L10N_1/VREF_1,VREF,1
+A,16,A16,IO_L01N_1/VRP_1,DCI,IO_L01N_1/VRP_1,DCI,IO_L01N_1/VRP_1,DCI,1
+A,17,A17,IO_L01P_1/VRN_1,DCI,IO_L01P_1/VRN_1,DCI,IO_L01P_1/VRN_1,DCI,1
+A,18,A18,GND,GND,GND,GND,GND,GND,N/A
+B,1,B1,IO_L16P_7/VREF_7,VREF,IO_L16P_7/VREF_7,VREF,IO_L16P_7/VREF_7,VREF,7
+B,2,B2,GND,GND,GND,GND,GND,GND,N/A
+B,3,B3,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+B,4,B4,IO_L09N_0,I/O,IO_L09N_0,I/O,IO_L09N_0,I/O,0
+B,5,B5,IO_L25N_0,I/O,IO_L25N_0,I/O,IO_L25N_0,I/O,0
+B,6,B6,IO_L25P_0,I/O,IO_L25P_0,I/O,IO_L25P_0,I/O,0
+B,7,B7,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+B,8,B8,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+B,9,B9,IO_L31N_0,I/O,IO_L31N_0,I/O,IO_L31N_0,I/O,0
+B,10,B10,IO_L31P_1,I/O,IO_L31P_1,I/O,IO_L31P_1,I/O,1
+B,11,B11,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+B,12,B12,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+B,13,B13,IO,I/O,IO,I/O,IO,I/O,1
+B,14,B14,IO_L16P_1,I/O,IO_L16P_1,I/O,IO_L16P_1,I/O,1
+B,15,B15,IO_L10P_1,I/O,IO_L10P_1,I/O,IO_L10P_1,I/O,1
+B,16,B16,TMS,JTAG,TMS,JTAG,TMS,JTAG,VCCAUX
+B,17,B17,GND,GND,GND,GND,GND,GND,N/A
+B,18,B18,IO_L16N_2,I/O,IO_L16N_2,I/O,IO_L16N_2,I/O,2
+C,1,C1,IO_L16N_7,I/O,IO_L16N_7,I/O,IO_L16N_7,I/O,7
+C,2,C2,IO_L01P_7/VRN_7,DCI,IO_L01P_7/VRN_7,DCI,IO_L01P_7/VRN_7,DCI,7
+C,3,C3,IO_L01N_7/VRP_7,DCI,IO_L01N_7/VRP_7,DCI,IO_L01N_7/VRP_7,DCI,7
+C,4,C4,IO_L09P_0,I/O,IO_L09P_0,I/O,IO_L09P_0,I/O,0
+C,5,C5,IO_L10N_0,I/O,IO_L10N_0,I/O,IO_L10N_0,I/O,0
+C,6,C6,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+C,7,C7,IO_L27N_0,I/O,IO_L27N_0,I/O,IO_L27N_0,I/O,0
+C,8,C8,IO_L28N_0,I/O,IO_L28N_0,I/O,IO_L28N_0,I/O,0
+C,9,C9,GND,GND,GND,GND,GND,GND,N/A
+C,10,C10,GND,GND,GND,GND,GND,GND,N/A
+C,11,C11,IO_L30N_1,I/O,IO_L30N_1,I/O,IO_L30N_1,I/O,1
+C,12,C12,IO_L28N_1,I/O,IO_L28N_1,I/O,IO_L28N_1,I/O,1
+C,13,C13,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+C,14,C14,IO_L15N_1,I/O,IO_L15N_1,I/O,IO_L15N_1,I/O,1
+C,15,C15,IO_L15P_1,I/O,IO_L15P_1,I/O,IO_L15P_1,I/O,1
+C,16,C16,IO_L01N_2/VRP_2,DCI,IO_L01N_2/VRP_2,DCI,IO_L01N_2/VRP_2,DCI,2
+C,17,C17,IO_L01P_2/VRN_2,DCI,IO_L01P_2/VRN_2,DCI,IO_L01P_2/VRN_2,DCI,2
+C,18,C18,IO_L16P_2,I/O,IO_L16P_2,I/O,IO_L16P_2,I/O,2
+D,1,D1,IO_L17N_7,I/O,IO_L17N_7,I/O,IO_L17N_7,I/O,7
+D,2,D2,IO_L17P_7,I/O,IO_L17P_7,I/O,IO_L17P_7,I/O,7
+D,3,D3,IO_L19P_7,I/O,IO_L19P_7,I/O,IO_L19P_7,I/O,7
+D,4,D4,TDI,JTAG,TDI,JTAG,TDI,JTAG,VCCAUX
+D,5,D5,IO_L10P_0,I/O,IO_L10P_0,I/O,IO_L10P_0,I/O,0
+D,6,D6,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+D,7,D7,IO_L27P_0,I/O,IO_L27P_0,I/O,IO_L27P_0,I/O,0
+D,8,D8,IO_L28P_0,I/O,IO_L28P_0,I/O,IO_L28P_0,I/O,0
+D,9,D9,IO,I/O,IO,I/O,IO,I/O,0
+D,10,D10,IO,I/O,IO,I/O,IO,I/O,1
+D,11,D11,IO_L30P_1,I/O,IO_L30P_1,I/O,IO_L30P_1,I/O,1
+D,12,D12,IO_L28P_1,I/O,IO_L28P_1,I/O,IO_L28P_1,I/O,1
+D,13,D13,IO_L24P_1,I/O,IO_L24P_1,I/O,IO_L24P_1,I/O,1
+D,14,D14,IO_L24N_1,I/O,IO_L24N_1,I/O,IO_L24N_1,I/O,1
+D,15,D15,TDO,JTAG,TDO,JTAG,TDO,JTAG,VCCAUX
+D,16,D16,IO_L19N_2,I/O,IO_L19N_2,I/O,IO_L19N_2,I/O,2
+D,17,D17,IO_L17N_2,I/O,IO_L17N_2,I/O,IO_L17N_2,I/O,2
+D,18,D18,IO_L17P_2/VREF_2,VREF,IO_L17P_2/VREF_2,VREF,IO_L17P_2/VREF_2,VREF,2
+E,1,E1,IO_L20P_7,I/O,IO_L20P_7,I/O,IO_L20P_7,I/O,7
+E,2,E2,IO_L20N_7,I/O,IO_L20N_7,I/O,IO_L20N_7,I/O,7
+E,3,E3,IO_L19N_7/VREF_7,VREF,IO_L19N_7/VREF_7,VREF,IO_L19N_7/VREF_7,VREF,7
+E,4,E4,IO_L21N_7,I/O,IO_L21N_7,I/O,IO_L21N_7,I/O,7
+E,5,E5,PROG_B,CONFIG,PROG_B,CONFIG,PROG_B,CONFIG,VCCAUX
+E,6,E6,HSWAP_EN,CONFIG,HSWAP_EN,CONFIG,HSWAP_EN,CONFIG,VCCAUX
+E,7,E7,IO,I/O,IO,I/O,IO,I/O,0
+E,8,E8,IO_L29N_0,I/O,IO_L29N_0,I/O,IO_L29N_0,I/O,0
+E,9,E9,IO_L32N_0/GCLK7,GCLK,IO_L32N_0/GCLK7,GCLK,IO_L32N_0/GCLK7,GCLK,0
+E,10,E10,IO_L32N_1/GCLK5,GCLK,IO_L32N_1/GCLK5,GCLK,IO_L32N_1/GCLK5,GCLK,1
+E,11,E11,IO_L29P_1,I/O,IO_L29P_1,I/O,IO_L29P_1,I/O,1
+E,12,E12,IO_L27P_1,I/O,IO_L27P_1,I/O,IO_L27P_1,I/O,1
+E,13,E13,IO_L27N_1,I/O,IO_L27N_1,I/O,IO_L27N_1,I/O,1
+E,14,E14,TCK,JTAG,TCK,JTAG,TCK,JTAG,VCCAUX
+E,15,E15,IO_L21P_2,I/O,IO_L21P_2,I/O,IO_L21P_2,I/O,2
+E,16,E16,IO_L19P_2,I/O,IO_L19P_2,I/O,IO_L19P_2,I/O,2
+E,17,E17,IO_L20N_2,I/O,IO_L20N_2,I/O,IO_L20N_2,I/O,2
+E,18,E18,IO_L20P_2,I/O,IO_L20P_2,I/O,IO_L20P_2,I/O,2
+F,1,F1,GND,GND,GND,GND,GND,GND,N/A
+F,2,F2,IO_L23P_7,I/O,IO_L23P_7,I/O,IO_L23P_7,I/O,7
+F,3,F3,VCCO_7,VCCO,VCCO_7,VCCO,VCCO_7,VCCO,7
+F,4,F4,IO_L21P_7,I/O,IO_L21P_7,I/O,IO_L21P_7,I/O,7
+F,5,F5,IO_L22P_7,I/O,IO_L22P_7,I/O,IO_L22P_7,I/O,7
+F,6,F6,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+F,7,F7,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+F,8,F8,IO_L29P_0,I/O,IO_L29P_0,I/O,IO_L29P_0,I/O,0
+F,9,F9,IO_L32P_0/GCLK6,GCLK,IO_L32P_0/GCLK6,GCLK,IO_L32P_0/GCLK6,GCLK,0
+F,10,F10,IO_L32P_1/GCLK4,GCLK,IO_L32P_1/GCLK4,GCLK,IO_L32P_1/GCLK4,GCLK,1
+F,11,F11,IO_L29N_1,I/O,IO_L29N_1,I/O,IO_L29N_1,I/O,1
+F,12,F12,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+F,13,F13,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+F,14,F14,IO_L22N_2,I/O,IO_L22N_2,I/O,IO_L22N_2,I/O,2
+F,15,F15,IO_L21N_2,I/O,IO_L21N_2,I/O,IO_L21N_2,I/O,2
+F,16,F16,VCCO_2,VCCO,VCCO_2,VCCO,VCCO_2,VCCO,2
+F,17,F17,IO_L23P_2,I/O,IO_L23P_2,I/O,IO_L23P_2,I/O,2
+F,18,F18,GND,GND,GND,GND,GND,GND,N/A
+G,1,G1,IO_L23N_7,I/O,IO_L23N_7,I/O,IO_L23N_7,I/O,7
+G,2,G2,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+G,3,G3,IO_L24P_7,I/O,IO_L24P_7,I/O,IO_L24P_7,I/O,7
+G,4,G4,IO_L24N_7,I/O,IO_L24N_7,I/O,IO_L24N_7,I/O,7
+G,5,G5,IO_L22N_7,I/O,IO_L22N_7,I/O,IO_L22N_7,I/O,7
+G,6,G6,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+G,7,G7,GND,GND,GND,GND,GND,GND,N/A
+G,8,G8,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+G,9,G9,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+G,10,G10,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+G,11,G11,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+G,12,G12,GND,GND,GND,GND,GND,GND,N/A
+G,13,G13,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+G,14,G14,IO_L22P_2,I/O,IO_L22P_2,I/O,IO_L22P_2,I/O,2
+G,15,G15,IO_L24N_2,I/O,IO_L24N_2,I/O,IO_L24N_2,I/O,2
+G,16,G16,IO_L24P_2,I/O,IO_L24P_2,I/O,IO_L24P_2,I/O,2
+G,17,G17,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+G,18,G18,IO_L23N_2/VREF_2,VREF,IO_L23N_2/VREF_2,VREF,IO_L23N_2/VREF_2,VREF,2
+H,1,H1,IO_L35N_7,I/O,IO_L35N_7,I/O,IO_L35N_7,I/O,7
+H,2,H2,IO_L35P_7,I/O,IO_L35P_7,I/O,IO_L35P_7,I/O,7
+H,3,H3,IO_L34P_7,I/O,IO_L34P_7,I/O,IO_L34P_7,I/O,7
+H,4,H4,IO_L34N_7,I/O,IO_L34N_7,I/O,IO_L34N_7,I/O,7
+H,5,H5,IO_L27N_7,I/O,IO_L27N_7,I/O,IO_L27N_7,I/O,7
+H,6,H6,IO_L27P_7/VREF_7,VREF,IO_L27P_7/VREF_7,VREF,IO_L27P_7/VREF_7,VREF,7
+H,7,H7,VCCO_7,VCCO,VCCO_7,VCCO,VCCO_7,VCCO,7
+H,8,H8,GND,GND,GND,GND,GND,GND,N/A
+H,9,H9,GND,GND,GND,GND,GND,GND,N/A
+H,10,H10,GND,GND,GND,GND,GND,GND,N/A
+H,11,H11,GND,GND,GND,GND,GND,GND,N/A
+H,12,H12,VCCO_2,VCCO,VCCO_2,VCCO,VCCO_2,VCCO,2
+H,13,H13,IO_L27N_2,I/O,IO_L27N_2,I/O,IO_L27N_2,I/O,2
+H,14,H14,IO_L27P_2,I/O,IO_L27P_2,I/O,IO_L27P_2,I/O,2
+H,15,H15,IO_L34P_2,I/O,IO_L34P_2,I/O,IO_L34P_2,I/O,2
+H,16,H16,IO_L34N_2/VREF_2,VREF,IO_L34N_2/VREF_2,VREF,IO_L34N_2/VREF_2,VREF,2
+H,17,H17,IO_L35N_2,I/O,IO_L35N_2,I/O,IO_L35N_2,I/O,2
+H,18,H18,IO_L35P_2,I/O,IO_L35P_2,I/O,IO_L35P_2,I/O,2
+J,1,J1,IO_L39N_7,I/O,IO_L39N_7,I/O,IO_L39N_7,I/O,7
+J,2,J2,IO_L39P_7,I/O,IO_L39P_7,I/O,IO_L39P_7,I/O,7
+J,3,J3,GND,GND,GND,GND,GND,GND,N/A
+J,4,J4,IO_L40P_7,I/O,IO_L40P_7,I/O,IO_L40P_7,I/O,7
+J,5,J5,IO_L40N_7/VREF_7,VREF,IO_L40N_7/VREF_7,VREF,IO_L40N_7/VREF_7,VREF,7
+J,6,J6,IO,I/O,IO,I/O,IO,I/O,7
+J,7,J7,VCCO_7,VCCO,VCCO_7,VCCO,VCCO_7,VCCO,7
+J,8,J8,GND,GND,GND,GND,GND,GND,N/A
+J,11,J11,GND,GND,GND,GND,GND,GND,N/A
+J,12,J12,VCCO_2,VCCO,VCCO_2,VCCO,VCCO_2,VCCO,2
+J,13,J13,IO,I/O,IO,I/O,IO,I/O,2
+J,14,J14,IO_L40P_2/VREF_2,VREF,IO_L40P_2/VREF_2,VREF,IO_L40P_2/VREF_2,VREF,2
+J,15,J15,IO_L40N_2,I/O,IO_L40N_2,I/O,IO_L40N_2,I/O,2
+J,16,J16,GND,GND,GND,GND,GND,GND,N/A
+J,17,J17,IO_L39P_2,I/O,IO_L39P_2,I/O,IO_L39P_2,I/O,2
+J,18,J18,IO_L39N_2,I/O,IO_L39N_2,I/O,IO_L39N_2,I/O,2
+K,1,K1,IO_L40N_6,I/O,IO_L40N_6,I/O,IO_L40N_6,I/O,6
+K,2,K2,IO_L40P_6/VREF_6,VREF,IO_L40P_6/VREF_6,VREF,IO_L40P_6/VREF_6,VREF,6
+K,3,K3,GND,GND,GND,GND,GND,GND,N/A
+K,4,K4,IO_L39P_6,I/O,IO_L39P_6,I/O,IO_L39P_6,I/O,6
+K,5,K5,IO_L39N_6,I/O,IO_L39N_6,I/O,IO_L39N_6,I/O,6
+K,6,K6,IO,I/O,IO,I/O,IO,I/O,6
+K,7,K7,VCCO_6,VCCO,VCCO_6,VCCO,VCCO_6,VCCO,6
+K,8,K8,GND,GND,GND,GND,GND,GND,N/A
+K,11,K11,GND,GND,GND,GND,GND,GND,N/A
+K,12,K12,VCCO_3,VCCO,VCCO_3,VCCO,VCCO_3,VCCO,3
+K,13,K13,IO_L39N_3,I/O,IO_L39N_3,I/O,IO_L39N_3,I/O,3
+K,14,K14,IO_L39P_3,I/O,IO_L39P_3,I/O,IO_L39P_3,I/O,3
+K,15,K15,IO,I/O,IO,I/O,IO,I/O,3
+K,16,K16,GND,GND,GND,GND,GND,GND,N/A
+K,17,K17,IO_L40N_3/VREF_3,VREF,IO_L40N_3/VREF_3,VREF,IO_L40N_3/VREF_3,VREF,3
+K,18,K18,IO_L40P_3,I/O,IO_L40P_3,I/O,IO_L40P_3,I/O,3
+L,1,L1,IO_L35P_6,I/O,IO_L35P_6,I/O,IO_L35P_6,I/O,6
+L,2,L2,IO_L35N_6,I/O,IO_L35N_6,I/O,IO_L35N_6,I/O,6
+L,3,L3,IO_L34N_6/VREF_6,VREF,IO_L34N_6/VREF_6,VREF,IO_L34N_6/VREF_6,VREF,6
+L,4,L4,IO_L34P_6,I/O,IO_L34P_6,I/O,IO_L34P_6,I/O,6
+L,5,L5,IO_L27P_6,I/O,IO_L27P_6,I/O,IO_L27P_6,I/O,6
+L,6,L6,IO_L27N_6,I/O,IO_L27N_6,I/O,IO_L27N_6,I/O,6
+L,7,L7,VCCO_6,VCCO,VCCO_6,VCCO,VCCO_6,VCCO,6
+L,8,L8,GND,GND,GND,GND,GND,GND,N/A
+L,9,L9,GND,GND,GND,GND,GND,GND,N/A
+L,10,L10,GND,GND,GND,GND,GND,GND,N/A
+L,11,L11,GND,GND,GND,GND,GND,GND,N/A
+L,12,L12,VCCO_3,VCCO,VCCO_3,VCCO,VCCO_3,VCCO,3
+L,13,L13,IO_L27P_3,I/O,IO_L27P_3,I/O,IO_L27P_3,I/O,3
+L,14,L14,IO_L27N_3,I/O,IO_L27N_3,I/O,IO_L27N_3,I/O,3
+L,15,L15,IO_L34N_3,I/O,IO_L34N_3,I/O,IO_L34N_3,I/O,3
+L,16,L16,IO_L34P_3/VREF_3,VREF,IO_L34P_3/VREF_3,VREF,IO_L34P_3/VREF_3,VREF,3
+L,17,L17,IO_L35P_3,I/O,IO_L35P_3,I/O,IO_L35P_3,I/O,3
+L,18,L18,IO_L35N_3,I/O,IO_L35N_3,I/O,IO_L35N_3,I/O,3
+M,1,M1,IO_L24P_6,I/O,IO_L24P_6,I/O,IO_L24P_6,I/O,6
+M,2,M2,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+M,3,M3,IO_L23N_6,I/O,IO_L23N_6,I/O,IO_L23N_6,I/O,6
+M,4,M4,IO_L23P_6,I/O,IO_L23P_6,I/O,IO_L23P_6,I/O,6
+M,5,M5,IO_L22P_6,I/O,IO_L22P_6,I/O,IO_L22P_6,I/O,6
+M,6,M6,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+M,7,M7,GND,GND,GND,GND,GND,GND,N/A
+M,8,M8,VCCO_5,VCCO,VCCO_5,VCCO,VCCO_5,VCCO,5
+M,9,M9,VCCO_5,VCCO,VCCO_5,VCCO,VCCO_5,VCCO,5
+M,10,M10,VCCO_4,VCCO,VCCO_4,VCCO,VCCO_4,VCCO,4
+M,11,M11,VCCO_4,VCCO,VCCO_4,VCCO,VCCO_4,VCCO,4
+M,12,M12,GND,GND,GND,GND,GND,GND,N/A
+M,13,M13,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+M,14,M14,IO_L22N_3,I/O,IO_L22N_3,I/O,IO_L22N_3,I/O,3
+M,15,M15,IO_L23N_3,I/O,IO_L23N_3,I/O,IO_L23N_3,I/O,3
+M,16,M16,IO_L23P_3/VREF_3,VREF,IO_L23P_3/VREF_3,VREF,IO_L23P_3/VREF_3,VREF,3
+M,17,M17,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+M,18,M18,IO_L24N_3,I/O,IO_L24N_3,I/O,IO_L24N_3,I/O,3
+N,1,N1,GND,GND,GND,GND,GND,GND,N/A
+N,2,N2,IO_L24N_6/VREF_6,VREF,IO_L24N_6/VREF_6,VREF,IO_L24N_6/VREF_6,VREF,6
+N,3,N3,VCCO_6,VCCO,VCCO_6,VCCO,VCCO_6,VCCO,6
+N,4,N4,IO_L21N_6,I/O,IO_L21N_6,I/O,IO_L21N_6,I/O,6
+N,5,N5,IO_L22N_6,I/O,IO_L22N_6,I/O,IO_L22N_6,I/O,6
+N,6,N6,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+N,7,N7,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+N,8,N8,IO,I/O,IO,I/O,IO,I/O,5
+N,9,N9,IO_L32N_5/GCLK3,GCLK,IO_L32N_5/GCLK3,GCLK,IO_L32N_5/GCLK3,GCLK,5
+N,10,N10,IO_L32N_4/GCLK1,GCLK,IO_L32N_4/GCLK1,GCLK,IO_L32N_4/GCLK1,GCLK,4
+N,11,N11,IO_L30N_4/D2,DUAL,IO_L30N_4/D2,DUAL,IO_L30N_4/D2,DUAL,4
+N,12,N12,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+N,13,N13,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,VCCINT,N/A
+N,14,N14,IO_L22P_3,I/O,IO_L22P_3,I/O,IO_L22P_3,I/O,3
+N,15,N15,IO_L21P_3,I/O,IO_L21P_3,I/O,IO_L21P_3,I/O,3
+N,16,N16,VCCO_3,VCCO,VCCO_3,VCCO,VCCO_3,VCCO,3
+N,17,N17,IO_L24P_3,I/O,IO_L24P_3,I/O,IO_L24P_3,I/O,3
+N,18,N18,GND,GND,GND,GND,GND,GND,N/A
+P,1,P1,IO_L20P_6,I/O,IO_L20P_6,I/O,IO_L20P_6,I/O,6
+P,2,P2,IO_L20N_6,I/O,IO_L20N_6,I/O,IO_L20N_6,I/O,6
+P,3,P3,IO_L19P_6,I/O,IO_L19P_6,I/O,IO_L19P_6,I/O,6
+P,4,P4,IO_L21P_6,I/O,IO_L21P_6,I/O,IO_L21P_6,I/O,6
+P,5,P5,M0,CONFIG,M0,CONFIG,M0,CONFIG,VCCAUX
+P,6,P6,IO_L27N_5/VREF_5,VREF,IO_L27N_5/VREF_5,VREF,IO_L27N_5/VREF_5,VREF,5
+P,7,P7,IO_L27P_5,I/O,IO_L27P_5,I/O,IO_L27P_5,I/O,5
+P,8,P8,IO,I/O,IO,I/O,IO,I/O,5
+P,9,P9,IO_L32P_5/GCLK2,GCLK,IO_L32P_5/GCLK2,GCLK,IO_L32P_5/GCLK2,GCLK,5
+P,10,P10,IO_L32P_4/GCLK0,GCLK,IO_L32P_4/GCLK0,GCLK,IO_L32P_4/GCLK0,GCLK,4
+P,11,P11,IO_L30P_4/D3,DUAL,IO_L30P_4/D3,DUAL,IO_L30P_4/D3,DUAL,4
+P,12,P12,IO,I/O,IO,I/O,IO,I/O,4
+P,13,P13,IO_L25P_4,I/O,IO_L25P_4,I/O,IO_L25P_4,I/O,4
+P,14,P14,IO_L06N_4/VREF_4,VREF,IO_L06N_4/VREF_4,VREF,IO_L06N_4/VREF_4,VREF,4
+P,15,P15,IO_L21N_3,I/O,IO_L21N_3,I/O,IO_L21N_3,I/O,3
+P,16,P16,IO_L17N_3,I/O,IO_L17N_3,I/O,IO_L17N_3,I/O,3
+P,17,P17,IO_L20P_3,I/O,IO_L20P_3,I/O,IO_L20P_3,I/O,3
+P,18,P18,IO_L20N_3,I/O,IO_L20N_3,I/O,IO_L20N_3,I/O,3
+R,1,R1,IO_L17P_6/VREF_6,VREF,IO_L17P_6/VREF_6,VREF,IO_L17P_6/VREF_6,VREF,6
+R,2,R2,IO_L17N_6,I/O,IO_L17N_6,I/O,IO_L17N_6,I/O,6
+R,3,R3,IO_L19N_6,I/O,IO_L19N_6,I/O,IO_L19N_6,I/O,6
+R,4,R4,M2,CONFIG,M2,CONFIG,M2,CONFIG,VCCAUX
+R,5,R5,IO_L15P_5,I/O,IO_L15P_5,I/O,IO_L15P_5,I/O,5
+R,6,R6,IO_L15N_5,I/O,IO_L15N_5,I/O,IO_L15N_5,I/O,5
+R,7,R7,IO_L28N_5/D6,DUAL,IO_L28N_5/D6,DUAL,IO_L28N_5/D6,DUAL,5
+R,8,R8,IO_L30N_5,I/O,IO_L30N_5,I/O,IO_L30N_5,I/O,5
+R,9,R9,IO/VREF_5,VREF,IO/VREF_5,VREF,IO/VREF_5,VREF,5
+R,10,R10,IO/VREF_4,VREF,IO/VREF_4,VREF,IO/VREF_4,VREF,4
+R,11,R11,IO_L29N_4,I/O,IO_L29N_4,I/O,IO_L29N_4,I/O,4
+R,12,R12,IO_L27P_4/D1,DUAL,IO_L27P_4/D1,DUAL,IO_L27P_4/D1,DUAL,4
+R,13,R13,IO_L25N_4,I/O,IO_L25N_4,I/O,IO_L25N_4,I/O,4
+R,14,R14,IO_L06P_4,I/O,IO_L06P_4,I/O,IO_L06P_4,I/O,4
+R,15,R15,DONE,CONFIG,DONE,CONFIG,DONE,CONFIG,VCCAUX
+R,16,R16,IO_L17P_3/VREF_3,VREF,IO_L17P_3/VREF_3,VREF,IO_L17P_3/VREF_3,VREF,3
+R,17,R17,IO_L19N_3,I/O,IO_L19N_3,I/O,IO_L19N_3,I/O,3
+R,18,R18,IO_L19P_3,I/O,IO_L19P_3,I/O,IO_L19P_3,I/O,3
+T,1,T1,IO_L16P_6,I/O,IO_L16P_6,I/O,IO_L16P_6,I/O,6
+T,2,T2,IO_L01P_6/VRN_6,DCI,IO_L01P_6/VRN_6,DCI,IO_L01P_6/VRN_6,DCI,6
+T,3,T3,IO_L01N_6/VRP_6,DCI,IO_L01N_6/VRP_6,DCI,IO_L01N_6/VRP_6,DCI,6
+T,4,T4,IO_L06P_5,I/O,IO_L06P_5,I/O,IO_L06P_5,I/O,5
+T,5,T5,IO_L06N_5,I/O,IO_L06N_5,I/O,IO_L06N_5,I/O,5
+T,6,T6,VCCO_5,VCCO,VCCO_5,VCCO,VCCO_5,VCCO,5
+T,7,T7,IO_L28P_5/D7,DUAL,IO_L28P_5/D7,DUAL,IO_L28P_5/D7,DUAL,5
+T,8,T8,IO_L30P_5,I/O,IO_L30P_5,I/O,IO_L30P_5,I/O,5
+T,9,T9,GND,GND,GND,GND,GND,GND,N/A
+T,10,T10,GND,GND,GND,GND,GND,GND,N/A
+T,11,T11,IO_L29P_4,I/O,IO_L29P_4,I/O,IO_L29P_4,I/O,4
+T,12,T12,IO_L27N_4/DIN/D0,DUAL,IO_L27N_4/DIN/D0,DUAL,IO_L27N_4/DIN/D0,DUAL,4
+T,13,T13,VCCO_4,VCCO,VCCO_4,VCCO,VCCO_4,VCCO,4
+T,14,T14,IO_L10N_4,I/O,IO_L10N_4,I/O,IO_L10N_4,I/O,4
+T,15,T15,CCLK,CONFIG,CCLK,CONFIG,CCLK,CONFIG,VCCAUX
+T,16,T16,IO_L01P_3/VRN_3,DCI,IO_L01P_3/VRN_3,DCI,IO_L01P_3/VRN_3,DCI,3
+T,17,T17,IO_L01N_3/VRP_3,DCI,IO_L01N_3/VRP_3,DCI,IO_L01N_3/VRP_3,DCI,3
+T,18,T18,IO_L16N_3,I/O,IO_L16N_3,I/O,IO_L16N_3,I/O,3
+U,1,U1,IO_L16N_6,I/O,IO_L16N_6,I/O,IO_L16N_6,I/O,6
+U,2,U2,GND,GND,GND,GND,GND,GND,N/A
+U,3,U3,M1,CONFIG,M1,CONFIG,M1,CONFIG,VCCAUX
+U,4,U4,IO_L10P_5/VRN_5,DCI,IO_L10P_5/VRN_5,DCI,IO_L10P_5/VRN_5,DCI,5
+U,5,U5,IO_L16P_5,I/O,IO_L16P_5,I/O,IO_L16P_5,I/O,5
+U,6,U6,IO,I/O,IO,I/O,IO,I/O,5
+U,7,U7,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+U,8,U8,VCCO_5,VCCO,VCCO_5,VCCO,VCCO_5,VCCO,5
+U,9,U9,IO_L31N_5/D4,DUAL,IO_L31N_5/D4,DUAL,IO_L31N_5/D4,DUAL,5
+U,10,U10,IO_L31N_4/INIT_B,DUAL,IO_L31N_4/INIT_B,DUAL,IO_L31N_4/INIT_B,DUAL,4
+U,11,U11,VCCO_4,VCCO,VCCO_4,VCCO,VCCO_4,VCCO,4
+U,12,U12,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+U,13,U13,IO/VREF_4,VREF,IO/VREF_4,VREF,IO/VREF_4,VREF,4
+U,14,U14,IO_L10P_4,I/O,IO_L10P_4,I/O,IO_L10P_4,I/O,4
+U,15,U15,IO_L09N_4,I/O,IO_L09N_4,I/O,IO_L09N_4,I/O,4
+U,16,U16,IO_L01N_4/VRP_4,DCI,IO_L01N_4/VRP_4,DCI,IO_L01N_4/VRP_4,DCI,4
+U,17,U17,GND,GND,GND,GND,GND,GND,N/A
+U,18,U18,IO_L16P_3,I/O,IO_L16P_3,I/O,IO_L16P_3,I/O,3
+V,1,V1,GND,GND,GND,GND,GND,GND,N/A
+V,2,V2,IO_L01P_5/CS_B,DUAL,IO_L01P_5/CS_B,DUAL,IO_L01P_5/CS_B,DUAL,5
+V,3,V3,IO_L01N_5/RDWR_B,DUAL,IO_L01N_5/RDWR_B,DUAL,IO_L01N_5/RDWR_B,DUAL,5
+V,4,V4,IO_L10N_5/VRP_5,DCI,IO_L10N_5/VRP_5,DCI,IO_L10N_5/VRP_5,DCI,5
+V,5,V5,IO_L16N_5,I/O,IO_L16N_5,I/O,IO_L16N_5,I/O,5
+V,6,V6,GND,GND,GND,GND,GND,GND,N/A
+V,7,V7,IO_L29P_5/VREF_5,VREF,IO_L29P_5/VREF_5,VREF,IO_L29P_5/VREF_5,VREF,5
+V,8,V8,IO_L29N_5,I/O,IO_L29N_5,I/O,IO_L29N_5,I/O,5
+V,9,V9,IO_L31P_5/D5,DUAL,IO_L31P_5/D5,DUAL,IO_L31P_5/D5,DUAL,5
+V,10,V10,IO_L31P_4/DOUT/BUSY,DUAL,IO_L31P_4/DOUT/BUSY,DUAL,IO_L31P_4/DOUT/BUSY,DUAL,4
+V,11,V11,IO_L28P_4,I/O,IO_L28P_4,I/O,IO_L28P_4,I/O,4
+V,12,V12,IO_L28N_4,I/O,IO_L28N_4,I/O,IO_L28N_4,I/O,4
+V,13,V13,GND,GND,GND,GND,GND,GND,N/A
+V,14,V14,IO,I/O,IO,I/O,IO,I/O,4
+V,15,V15,IO_L09P_4,I/O,IO_L09P_4,I/O,IO_L09P_4,I/O,4
+V,16,V16,IO_L01P_4/VRN_4,DCI,IO_L01P_4/VRN_4,DCI,IO_L01P_4/VRN_4,DCI,4
+V,17,V17,IO/VREF_4,VREF,IO/VREF_4,VREF,IO/VREF_4,VREF,4
+V,18,V18,GND,GND,GND,GND,GND,GND,N/A
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-CFG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-CFG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-CFG.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,39 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-CFG
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+E5 io line l PROG_B
+E6 io line l HSWAP_EN
+N11 io line r IO_L30N_4/D2
+P5 io line l M0
+P11 io line r IO_L30P_4/D3
+R4 io line l M2
+R7 io line r IO_L28N_5/D6
+R12 io line r IO_L27P_4/D1
+R15 io line l DONE
+T7 io line r IO_L28P_5/D7
+T12 io line r IO_L27N_4/DIN/D0
+T15 io line l CCLK
+U3 io line l M1
+U9 io line r IO_L31N_5/D4
+U10 io line r IO_L31N_4/INIT_B
+V2 io line r IO_L01P_5/CS_B
+V3 io line r IO_L01N_5/RDWR_B
+V9 io line r IO_L31P_5/D5
+V10 io line r IO_L31P_4/DOUT/BUSY
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-CLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-CLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-CLK.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-CLK
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+E9 clk clk l IO_L32N_0/GCLK7
+E10 clk clk l IO_L32N_1/GCLK5
+F9 clk clk l IO_L32P_0/GCLK6
+F10 clk clk l IO_L32P_1/GCLK4
+N9 clk clk l IO_L32N_5/GCLK3
+N10 clk clk l IO_L32N_4/GCLK1
+P9 clk clk l IO_L32P_5/GCLK2
+P10 clk clk l IO_L32P_4/GCLK0
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO0.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO0.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO0.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,48 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO0
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A2 io line l IO_L01N_0/VRP_0/DCI
+A3 io line l IO_L01P_0/VRN_0/DCI
+A4 io line l IO_L15N_0
+A5 io line l IO_L15P_0
+A7 io line l IO_L30N_0
+A8 io line l IO_L30P_0
+A9 io line r IO_L31P_0/VREF_0
+B3 io line r IO/VREF_0
+B4 io line l IO_L09N_0
+B5 io line l IO_L25N_0
+B6 io line l IO_L25P_0
+B8 pwr line b VCCO_0
+B9 io line l IO_L31N_0
+C4 io line l IO_L09P_0
+C5 io line l IO_L10N_0
+C6 pwr line b VCCO_0
+C7 io line l IO_L27N_0
+C8 io line l IO_L28N_0
+D5 io line l IO_L10P_0
+D6 io line r IO/VREF_0
+D7 io line l IO_L27P_0
+D8 io line l IO_L28P_0
+D9 io line l IO
+E7 io line l IO
+E8 io line l IO_L29N_0
+F8 io line l IO_L29P_0
+G8 pwr line b VCCO_0
+G9 pwr line b VCCO_0
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO1.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO1.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO1.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,48 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO1
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A10 io line r IO_L31N_1/VREF_1
+A11 io line l IO
+A12 io line r IO/VREF_1
+A14 io line l IO_L16N_1
+A15 io line r IO_L10N_1/VREF_1
+A16 io line l IO_L01N_1/VRP_1/DCI
+A17 io line l IO_L01P_1/VRN_1/DCI
+B10 io line l IO_L31P_1
+B11 pwr line b VCCO_1
+B13 io line l IO
+B14 io line l IO_L16P_1
+B15 io line l IO_L10P_1
+C11 io line l IO_L30N_1
+C12 io line l IO_L28N_1
+C13 pwr line b VCCO_1
+C14 io line l IO_L15N_1
+C15 io line l IO_L15P_1
+D10 io line l IO
+D11 io line l IO_L30P_1
+D12 io line l IO_L28P_1
+D13 io line l IO_L24P_1
+D14 io line l IO_L24N_1
+E11 io line l IO_L29P_1
+E12 io line l IO_L27P_1
+E13 io line l IO_L27N_1
+F11 io line l IO_L29N_1
+G10 pwr line b VCCO_1
+G11 pwr line b VCCO_1
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO2.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO2.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO2.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,52 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO2
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+B18 io line l IO_L16N_2
+C16 io line l IO_L01N_2/VRP_2/DCI
+C17 io line l IO_L01P_2/VRN_2/DCI
+C18 io line l IO_L16P_2
+D16 io line l IO_L19N_2
+D17 io line l IO_L17N_2
+D18 io line r IO_L17P_2/VREF_2
+E15 io line l IO_L21P_2
+E16 io line l IO_L19P_2
+E17 io line l IO_L20N_2
+E18 io line l IO_L20P_2
+F14 io line l IO_L22N_2
+F15 io line l IO_L21N_2
+F16 pwr line b VCCO_2
+F17 io line l IO_L23P_2
+G14 io line l IO_L22P_2
+G15 io line l IO_L24N_2
+G16 io line l IO_L24P_2
+G18 io line r IO_L23N_2/VREF_2
+H12 pwr line b VCCO_2
+H13 io line l IO_L27N_2
+H14 io line l IO_L27P_2
+H15 io line l IO_L34P_2
+H16 io line r IO_L34N_2/VREF_2
+H17 io line l IO_L35N_2
+H18 io line l IO_L35P_2
+J12 pwr line b VCCO_2
+J13 io line l IO
+J14 io line r IO_L40P_2/VREF_2
+J15 io line l IO_L40N_2
+J17 io line l IO_L39P_2
+J18 io line l IO_L39N_2
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO3.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO3.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO3.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,52 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO3
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+K12 pwr line b VCCO_3
+K13 io line l IO_L39N_3
+K14 io line l IO_L39P_3
+K15 io line l IO
+K17 io line r IO_L40N_3/VREF_3
+K18 io line l IO_L40P_3
+L12 pwr line b VCCO_3
+L13 io line l IO_L27P_3
+L14 io line l IO_L27N_3
+L15 io line l IO_L34N_3
+L16 io line r IO_L34P_3/VREF_3
+L17 io line l IO_L35P_3
+L18 io line l IO_L35N_3
+M14 io line l IO_L22N_3
+M15 io line l IO_L23N_3
+M16 io line r IO_L23P_3/VREF_3
+M18 io line l IO_L24N_3
+N14 io line l IO_L22P_3
+N15 io line l IO_L21P_3
+N16 pwr line b VCCO_3
+N17 io line l IO_L24P_3
+P15 io line l IO_L21N_3
+P16 io line l IO_L17N_3
+P17 io line l IO_L20P_3
+P18 io line l IO_L20N_3
+R16 io line r IO_L17P_3/VREF_3
+R17 io line l IO_L19N_3
+R18 io line l IO_L19P_3
+T16 io line l IO_L01P_3/VRN_3/DCI
+T17 io line l IO_L01N_3/VRP_3/DCI
+T18 io line l IO_L16N_3
+U18 io line l IO_L16P_3
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO4.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO4.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO4.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,43 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO4
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+M10 pwr line b VCCO_4
+M11 pwr line b VCCO_4
+P12 io line l IO
+P13 io line l IO_L25P_4
+P14 io line r IO_L06N_4/VREF_4
+R10 io line r IO/VREF_4
+R11 io line l IO_L29N_4
+R13 io line l IO_L25N_4
+R14 io line l IO_L06P_4
+T11 io line l IO_L29P_4
+T13 pwr line b VCCO_4
+T14 io line l IO_L10N_4
+U11 pwr line b VCCO_4
+U13 io line r IO/VREF_4
+U14 io line l IO_L10P_4
+U15 io line l IO_L09N_4
+U16 io line l IO_L01N_4/VRP_4/DCI
+V11 io line l IO_L28P_4
+V12 io line l IO_L28N_4
+V14 io line l IO
+V15 io line l IO_L09P_4
+V16 io line l IO_L01P_4/VRN_4/DCI
+V17 io line r IO/VREF_4
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO5.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO5.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO5.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,42 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO5
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+M8 pwr line b VCCO_5
+M9 pwr line b VCCO_5
+N8 io line l IO
+P6 io line r IO_L27N_5/VREF_5
+P7 io line l IO_L27P_5
+P8 io line l IO
+R5 io line l IO_L15P_5
+R6 io line l IO_L15N_5
+R8 io line l IO_L30N_5
+R9 io line r IO/VREF_5
+T4 io line l IO_L06P_5
+T5 io line l IO_L06N_5
+T6 pwr line b VCCO_5
+T8 io line l IO_L30P_5
+U4 io line l IO_L10P_5/VRN_5/DCI
+U5 io line l IO_L16P_5
+U6 io line l IO
+U8 pwr line b VCCO_5
+V4 io line l IO_L10N_5/VRP_5/DCI
+V5 io line l IO_L16N_5
+V7 io line r IO_L29P_5/VREF_5
+V8 io line l IO_L29N_5
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO6.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO6.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO6.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,52 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO6
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+K1 io line l IO_L40N_6
+K2 io line r IO_L40P_6/VREF_6
+K4 io line l IO_L39P_6
+K5 io line l IO_L39N_6
+K6 io line l IO
+K7 pwr line b VCCO_6
+L1 io line l IO_L35P_6
+L2 io line l IO_L35N_6
+L3 io line r IO_L34N_6/VREF_6
+L4 io line l IO_L34P_6
+L5 io line l IO_L27P_6
+L6 io line l IO_L27N_6
+L7 pwr line b VCCO_6
+M1 io line l IO_L24P_6
+M3 io line l IO_L23N_6
+M4 io line l IO_L23P_6
+M5 io line l IO_L22P_6
+N2 io line r IO_L24N_6/VREF_6
+N3 pwr line b VCCO_6
+N4 io line l IO_L21N_6
+N5 io line l IO_L22N_6
+P1 io line l IO_L20P_6
+P2 io line l IO_L20N_6
+P3 io line l IO_L19P_6
+P4 io line l IO_L21P_6
+R1 io line r IO_L17P_6/VREF_6
+R2 io line l IO_L17N_6
+R3 io line l IO_L19N_6
+T1 io line l IO_L16P_6
+T2 io line l IO_L01P_6/VRN_6/DCI
+T3 io line l IO_L01N_6/VRP_6/DCI
+U1 io line l IO_L16N_6
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO7.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO7.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-IO7.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,52 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-IO7
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+B1 io line r IO_L16P_7/VREF_7
+C1 io line l IO_L16N_7
+C2 io line l IO_L01P_7/VRN_7/DCI
+C3 io line l IO_L01N_7/VRP_7/DCI
+D1 io line l IO_L17N_7
+D2 io line l IO_L17P_7
+D3 io line l IO_L19P_7
+E1 io line l IO_L20P_7
+E2 io line l IO_L20N_7
+E3 io line r IO_L19N_7/VREF_7
+E4 io line l IO_L21N_7
+F2 io line l IO_L23P_7
+F3 pwr line b VCCO_7
+F4 io line l IO_L21P_7
+F5 io line l IO_L22P_7
+G1 io line l IO_L23N_7
+G3 io line l IO_L24P_7
+G4 io line l IO_L24N_7
+G5 io line l IO_L22N_7
+H1 io line l IO_L35N_7
+H2 io line l IO_L35P_7
+H3 io line l IO_L34P_7
+H4 io line l IO_L34N_7
+H5 io line l IO_L27N_7
+H6 io line r IO_L27P_7/VREF_7
+H7 pwr line b VCCO_7
+J1 io line l IO_L39N_7
+J2 io line l IO_L39P_7
+J4 io line l IO_L40P_7
+J5 io line r IO_L40N_7/VREF_7
+J6 io line l IO
+J7 pwr line b VCCO_7
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-JTAG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-JTAG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-JTAG.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,24 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-JTAG
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+B16 io line l TMS
+D4 io line l TDI
+D15 io line l TDO
+E14 io line l TCK
Added: usrp-hw/trunk/sym/generated/xc3sXX00fg320-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg320-PWR.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg320-PWR.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -0,0 +1,80 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-PWR
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A1 pwr line r GND
+A6 pwr line r GND
+A13 pwr line r GND
+A18 pwr line r GND
+B2 pwr line r GND
+B7 pwr line l VCCAUX
+B12 pwr line l VCCAUX
+B17 pwr line r GND
+C9 pwr line r GND
+C10 pwr line r GND
+F1 pwr line r GND
+F6 pwr line l VCCINT
+F7 pwr line l VCCINT
+F12 pwr line l VCCINT
+F13 pwr line l VCCINT
+F18 pwr line r GND
+G2 pwr line l VCCAUX
+G6 pwr line l VCCINT
+G7 pwr line r GND
+G12 pwr line r GND
+G13 pwr line l VCCINT
+G17 pwr line l VCCAUX
+H8 pwr line r GND
+H9 pwr line r GND
+H10 pwr line r GND
+H11 pwr line r GND
+J3 pwr line r GND
+J8 pwr line r GND
+J11 pwr line r GND
+J16 pwr line r GND
+K3 pwr line r GND
+K8 pwr line r GND
+K11 pwr line r GND
+K16 pwr line r GND
+L8 pwr line r GND
+L9 pwr line r GND
+L10 pwr line r GND
+L11 pwr line r GND
+M2 pwr line l VCCAUX
+M6 pwr line l VCCINT
+M7 pwr line r GND
+M12 pwr line r GND
+M13 pwr line l VCCINT
+M17 pwr line l VCCAUX
+N1 pwr line r GND
+N6 pwr line l VCCINT
+N7 pwr line l VCCINT
+N12 pwr line l VCCINT
+N13 pwr line l VCCINT
+N18 pwr line r GND
+T9 pwr line r GND
+T10 pwr line r GND
+U2 pwr line r GND
+U7 pwr line l VCCAUX
+U12 pwr line l VCCAUX
+U17 pwr line r GND
+V1 pwr line r GND
+V6 pwr line r GND
+V13 pwr line r GND
+V18 pwr line r GND
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-CFG.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,22 +18,22 @@
author=xilinxgen.py
numslots=0
[pins]
-A2 io line l PROG\_B
-B3 io line l HSWAP\_EN
-U12 io line r IO\_L30N\_4/D2
-V11 io line r IO\_L31P\_5/D5
-V12 io line r IO\_L30P\_4/D3
-W11 io line r IO\_L31N\_5/D4
-W12 io line r IO\_L31N\_4/INIT\_B
-Y4 io line r IO\_L01N\_5/RDWR\_B
-Y12 io line r IO\_L31P\_4/DOUT/BUSY
+A2 io line l PROG_B
+B3 io line l HSWAP_EN
+U12 io line r IO_L30N_4/D2
+V11 io line r IO_L31P_5/D5
+V12 io line r IO_L30P_4/D3
+W11 io line r IO_L31N_5/D4
+W12 io line r IO_L31N_4/INIT_B
+Y4 io line r IO_L01N_5/RDWR_B
+Y12 io line r IO_L31P_4/DOUT/BUSY
AA1 io line l M1
-AA3 io line r IO\_L01P\_5/CS\_B
-AA9 io line r IO\_L28P\_5/D7
-AA14 io line r IO\_L27N\_4/DIN/D0
+AA3 io line r IO_L01P_5/CS_B
+AA9 io line r IO_L28P_5/D7
+AA14 io line r IO_L27N_4/DIN/D0
AA22 io line l CCLK
AB2 io line l M0
AB3 io line l M2
-AB9 io line r IO\_L28N\_5/D6
-AB14 io line r IO\_L27P\_4/D1
+AB9 io line r IO_L28N_5/D6
+AB14 io line r IO_L27P_4/D1
AB21 io line l DONE
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-CLK.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,11 +18,11 @@
author=xilinxgen.py
numslots=0
[pins]
-A11 clk clk l IO\_L32P\_0/GCLK6
-B11 clk clk l IO\_L32N\_0/GCLK7
-B12 clk clk l IO\_L32N\_1/GCLK5
-C12 clk clk l IO\_L32P\_1/GCLK4
-Y11 clk clk l IO\_L32P\_5/GCLK2
-AA11 clk clk l IO\_L32N\_5/GCLK3
-AA12 clk clk l IO\_L32N\_4/GCLK1
-AB12 clk clk l IO\_L32P\_4/GCLK0
+A11 clk clk l IO_L32P_0/GCLK6
+B11 clk clk l IO_L32N_0/GCLK7
+B12 clk clk l IO_L32N_1/GCLK5
+C12 clk clk l IO_L32P_1/GCLK4
+Y11 clk clk l IO_L32P_5/GCLK2
+AA11 clk clk l IO_L32N_5/GCLK3
+AA12 clk clk l IO_L32N_4/GCLK1
+AB12 clk clk l IO_L32P_4/GCLK0
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO0.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,36 +18,46 @@
author=xilinxgen.py
numslots=0
[pins]
-A4 io line l IO\_L01P\_0/VRN\_0/DCI
-A5 io line l IO\_L09P\_0
-A7 io line r IO\_L19P\_0/400NC
-A8 io line l IO\_L24P\_0
-A9 io line l IO\_L27P\_0
+A3 io line r IO/VREF_0
+A4 io line l IO_L01P_0/VRN_0/DCI
+A5 io line l IO_L09P_0
+A7 io line r IO_L19P_0/400NC
+A8 io line l IO_L24P_0
+A9 io line l IO_L27P_0
A10 io line l IO
-B4 io line l IO\_L01N\_0/VRP\_0/DCI
-B5 io line l IO\_L09N\_0
-B6 io line l IO\_L15P\_0
-B7 io line r IO\_L19N\_0/400NC
-B8 io line l IO\_L24N\_0
-B9 io line l IO\_L27N\_0
-B10 io line l IO\_L29P\_0
-C5 io line l IO\_L06P\_0
-C6 io line l IO\_L15N\_0
-C10 io line l IO\_L29N\_0
-D5 io line l IO\_L06N\_0
-D6 io line l IO\_L10P\_0
-D7 io line l IO\_L16P\_0
-D8 io line r IO\_L22P\_0/400NC
+B4 io line l IO_L01N_0/VRP_0/DCI
+B5 io line l IO_L09N_0
+B6 io line l IO_L15P_0
+B7 io line r IO_L19N_0/400NC
+B8 io line l IO_L24N_0
+B9 io line l IO_L27N_0
+B10 io line l IO_L29P_0
+C5 io line l IO_L06P_0
+C6 io line l IO_L15N_0
+C7 io line r IO/VREF_0
+C8 pwr line b VCCO_0
+C10 io line l IO_L29N_0
+C11 io line r IO_L31P_0/VREF_0
+D5 io line l IO_L06N_0
+D6 io line l IO_L10P_0
+D7 io line l IO_L16P_0
+D8 io line r IO_L22P_0/400NC
D9 io line l IO
D10 io line l IO
-D11 io line l IO\_L31N\_0
-E6 io line l IO\_L10N\_0
-E7 io line l IO\_L16N\_0
-E8 io line r IO\_L22N\_0/400NC
-E9 io line l IO\_L25P\_0
-E10 io line l IO\_L28P\_0
-E11 io line l IO\_L30P\_0
+D11 io line l IO_L31N_0
+E5 io line r IO/VREF_0/400NC
+E6 io line l IO_L10N_0
+E7 io line l IO_L16N_0
+E8 io line r IO_L22N_0/400NC
+E9 io line l IO_L25P_0
+E10 io line l IO_L28P_0
+E11 io line l IO_L30P_0
F6 io line l IO
-F9 io line l IO\_L25N\_0
-F10 io line l IO\_L28N\_0
-F11 io line l IO\_L30N\_0
+F7 io line r IO/VREF_0
+F8 pwr line b VCCO_0
+F9 io line l IO_L25N_0
+F10 io line l IO_L28N_0
+F11 io line l IO_L30N_0
+G9 pwr line b VCCO_0
+G10 pwr line b VCCO_0
+G11 pwr line b VCCO_0
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO1.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -19,35 +19,45 @@
numslots=0
[pins]
A12 io line l IO
-A13 io line l IO\_L30N\_1
-A14 io line l IO\_L28N\_1
-A15 io line l IO\_L25P\_1
-A16 io line r IO\_L22N\_1/400NC
-B13 io line l IO\_L30P\_1
-B14 io line l IO\_L28P\_1
-B15 io line l IO\_L25N\_1
-B16 io line r IO\_L22P\_1/400NC
-B17 io line l IO\_L16N\_1
-B18 io line l IO\_L10P\_1
-B19 io line l IO\_L06P\_1
-B20 io line l IO\_L01P\_1/VRN\_1/DCI
-C13 io line l IO\_L29N\_1
-C16 io line r IO\_L19N\_1/400NC
-C17 io line l IO\_L16P\_1
-C18 io line l IO\_L09N\_1
-C19 io line l IO\_L01N\_1/VRP\_1/DCI
-D13 io line l IO\_L29P\_1
-D14 io line l IO\_L27N\_1
-D15 io line l IO\_L24N\_1
-D16 io line r IO\_L19P\_1/400NC
-D17 io line l IO\_L15N\_1
-D18 io line l IO\_L09P\_1
-E12 io line l IO\_L31P\_1
-E14 io line l IO\_L27P\_1
-E15 io line l IO\_L24P\_1
+A13 io line l IO_L30N_1
+A14 io line l IO_L28N_1
+A15 io line l IO_L25P_1
+A16 io line r IO_L22N_1/400NC
+A18 io line r IO_L10N_1/VREF_1
+A19 io line r IO_L06N_1/VREF_1
+B13 io line l IO_L30P_1
+B14 io line l IO_L28P_1
+B15 io line l IO_L25N_1
+B16 io line r IO_L22P_1/400NC
+B17 io line l IO_L16N_1
+B18 io line l IO_L10P_1
+B19 io line l IO_L06P_1
+B20 io line l IO_L01P_1/VRN_1/DCI
+C13 io line l IO_L29N_1
+C15 pwr line b VCCO_1
+C16 io line r IO_L19N_1/400NC
+C17 io line l IO_L16P_1
+C18 io line l IO_L09N_1
+C19 io line l IO_L01N_1/VRP_1/DCI
+D12 io line r IO_L31N_1/VREF_1
+D13 io line l IO_L29P_1
+D14 io line l IO_L27N_1
+D15 io line l IO_L24N_1
+D16 io line r IO_L19P_1/400NC
+D17 io line l IO_L15N_1
+D18 io line l IO_L09P_1
+E12 io line l IO_L31P_1
+E13 io line r IO/VREF_1
+E14 io line l IO_L27P_1
+E15 io line l IO_L24P_1
E16 io line l IO
-E17 io line l IO\_L15P\_1
+E17 io line l IO_L15P_1
F12 io line l IO
F13 io line l IO
+F14 io line r IO/VREF_1/400NC
+F15 pwr line b VCCO_1
F16 io line l IO
F17 io line l IO
+G12 pwr line b VCCO_1
+G13 pwr line b VCCO_1
+G14 pwr line b VCCO_1
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO2.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,42 +18,51 @@
author=xilinxgen.py
numslots=0
[pins]
-C20 io line l IO\_L01N\_2/VRP\_2/DCI
-C21 io line l IO\_L01P\_2/VRN\_2/DCI
+C20 io line l IO_L01N_2/VRP_2/DCI
+C21 io line l IO_L01P_2/VRN_2/DCI
C22 io line l IO
-D19 io line l IO\_L16P\_2
-D20 io line l IO\_L16N\_2
-D21 io line l IO\_L17N\_2
-E18 io line l IO\_L19N\_2
-E19 io line l IO\_L20N\_2
-E20 io line l IO\_L20P\_2
-E21 io line l IO\_L21N\_2
-E22 io line l IO\_L21P\_2
-F18 io line l IO\_L19P\_2
-F20 io line l IO\_L24N\_2
-F21 io line l IO\_L24P\_2
-G17 io line l IO\_L22N\_2
-G18 io line l IO\_L22P\_2
-G19 io line l IO\_L23P\_2
-G20 io line r IO\_L26N\_2/400NC
-G21 io line l IO\_L27N\_2
-G22 io line l IO\_L27P\_2
-H18 io line r IO\_L28N\_2/400NC
-H19 io line r IO\_L26P\_2/400NC
-H21 io line r IO\_L29N\_2/400NC
-H22 io line r IO\_L29P\_2/400NC
-J17 io line r IO\_L28P\_2/400NC
-J18 io line r IO\_L31N\_2/400NC
-J19 io line r IO\_L31P\_2/400NC
-J21 io line r IO\_L32N\_2/400NC
-J22 io line r IO\_L32P\_2/400NC
-K17 io line r IO\_L33N\_2/400NC
-K18 io line r IO\_L33P\_2/400NC
-K20 io line l IO\_L34P\_2
-K21 io line l IO\_L35N\_2
-K22 io line l IO\_L35P\_2
-L17 io line l IO\_L38N\_2
-L18 io line l IO\_L38P\_2
-L19 io line l IO\_L39N\_2
-L20 io line l IO\_L39P\_2
-L21 io line l IO\_L40N\_2
+D19 io line l IO_L16P_2
+D20 io line l IO_L16N_2
+D21 io line l IO_L17N_2
+D22 io line r IO_L17P_2/VREF_2
+E18 io line l IO_L19N_2
+E19 io line l IO_L20N_2
+E20 io line l IO_L20P_2
+E21 io line l IO_L21N_2
+E22 io line l IO_L21P_2
+F18 io line l IO_L19P_2
+F19 io line r IO_L23N_2/VREF_2
+F20 io line l IO_L24N_2
+F21 io line l IO_L24P_2
+G17 io line l IO_L22N_2
+G18 io line l IO_L22P_2
+G19 io line l IO_L23P_2
+G20 io line r IO_L26N_2/400NC
+G21 io line l IO_L27N_2
+G22 io line l IO_L27P_2
+H17 pwr line b VCCO_2
+H18 io line r IO_L28N_2/400NC
+H19 io line r IO_L26P_2/400NC
+H20 pwr line b VCCO_2
+H21 io line r IO_L29N_2/400NC
+H22 io line r IO_L29P_2/400NC
+J16 pwr line b VCCO_2
+J17 io line r IO_L28P_2/400NC
+J18 io line r IO_L31N_2/400NC
+J19 io line r IO_L31P_2/400NC
+J21 io line r IO_L32N_2/400NC
+J22 io line r IO_L32P_2/400NC
+K16 pwr line b VCCO_2
+K17 io line r IO_L33N_2/400NC
+K18 io line r IO_L33P_2/400NC
+K19 io line r IO_L34N_2/VREF_2
+K20 io line l IO_L34P_2
+K21 io line l IO_L35N_2
+K22 io line l IO_L35P_2
+L16 pwr line b VCCO_2
+L17 io line l IO_L38N_2
+L18 io line l IO_L38P_2
+L19 io line l IO_L39N_2
+L20 io line l IO_L39P_2
+L21 io line l IO_L40N_2
+L22 io line r IO_L40P_2/VREF_2
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO3.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,42 +18,51 @@
author=xilinxgen.py
numslots=0
[pins]
-M17 io line l IO\_L38P\_3
-M18 io line l IO\_L38N\_3
-M19 io line l IO\_L39P\_3
-M20 io line l IO\_L39N\_3
-M21 io line l IO\_L40P\_3
-N17 io line r IO\_L33P\_3/400NC
-N18 io line r IO\_L33N\_3/400NC
-N20 io line l IO\_L34N\_3
-N21 io line l IO\_L35P\_3
-N22 io line l IO\_L35N\_3
-P17 io line r IO\_L31P\_3/400NC
-P18 io line r IO\_L31N\_3/400NC
-P19 io line r IO\_L29N\_3/400NC
-P21 io line r IO\_L32P\_3/400NC
-P22 io line r IO\_L32N\_3/400NC
-R18 io line l IO\_L24N\_3
-R19 io line r IO\_L29P\_3/400NC
-R21 io line r IO\_L28P\_3/400NC
-R22 io line r IO\_L28N\_3/400NC
-T17 io line l IO\_L22N\_3
-T18 io line l IO\_L24P\_3
-T19 io line r IO\_L26P\_3/400NC
-T20 io line r IO\_L26N\_3/400NC
-T21 io line l IO\_L27P\_3
-T22 io line l IO\_L27N\_3
-U18 io line l IO\_L22P\_3
-U19 io line l IO\_L20N\_3
-U21 io line l IO\_L23N\_3
-V19 io line l IO\_L17N\_3
-V20 io line l IO\_L20P\_3
-V21 io line l IO\_L21P\_3
-V22 io line l IO\_L21N\_3
-W20 io line l IO\_L19P\_3
-W21 io line l IO\_L19N\_3
-W22 io line l IO\_L16N\_3
-Y19 io line l IO\_L01P\_3/VRN\_3/DCI
-Y20 io line l IO\_L01N\_3/VRP\_3/DCI
+M16 pwr line b VCCO_3
+M17 io line l IO_L38P_3
+M18 io line l IO_L38N_3
+M19 io line l IO_L39P_3
+M20 io line l IO_L39N_3
+M21 io line l IO_L40P_3
+M22 io line r IO_L40N_3/VREF_3
+N16 pwr line b VCCO_3
+N17 io line r IO_L33P_3/400NC
+N18 io line r IO_L33N_3/400NC
+N19 io line r IO_L34P_3/VREF_3
+N20 io line l IO_L34N_3
+N21 io line l IO_L35P_3
+N22 io line l IO_L35N_3
+P16 pwr line b VCCO_3
+P17 io line r IO_L31P_3/400NC
+P18 io line r IO_L31N_3/400NC
+P19 io line r IO_L29N_3/400NC
+P21 io line r IO_L32P_3/400NC
+P22 io line r IO_L32N_3/400NC
+R17 pwr line b VCCO_3
+R18 io line l IO_L24N_3
+R19 io line r IO_L29P_3/400NC
+R20 pwr line b VCCO_3
+R21 io line r IO_L28P_3/400NC
+R22 io line r IO_L28N_3/400NC
+T17 io line l IO_L22N_3
+T18 io line l IO_L24P_3
+T19 io line r IO_L26P_3/400NC
+T20 io line r IO_L26N_3/400NC
+T21 io line l IO_L27P_3
+T22 io line l IO_L27N_3
+U18 io line l IO_L22P_3
+U19 io line l IO_L20N_3
+U20 io line r IO_L23P_3/VREF_3
+U21 io line l IO_L23N_3
+V19 io line l IO_L17N_3
+V20 io line l IO_L20P_3
+V21 io line l IO_L21P_3
+V22 io line l IO_L21N_3
+W19 io line r IO_L17P_3/VREF_3
+W20 io line l IO_L19P_3
+W21 io line l IO_L19N_3
+W22 io line l IO_L16N_3
+Y19 io line l IO_L01P_3/VRN_3/DCI
+Y20 io line l IO_L01N_3/VRP_3/DCI
Y21 io line l IO
-Y22 io line l IO\_L16P\_3
+Y22 io line l IO_L16P_3
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO4.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,31 +18,41 @@
author=xilinxgen.py
numslots=0
[pins]
-U13 io line l IO\_L28N\_4
-U14 io line l IO\_L25N\_4
+T12 pwr line b VCCO_4
+T13 pwr line b VCCO_4
+T14 pwr line b VCCO_4
+U13 io line l IO_L28N_4
+U14 io line l IO_L25N_4
+U15 pwr line b VCCO_4
U16 io line l IO
U17 io line l IO
-V13 io line l IO\_L28P\_4
-V14 io line l IO\_L25P\_4
-V16 io line l IO\_L16N\_4
-V17 io line l IO\_L10N\_4
+V13 io line l IO_L28P_4
+V14 io line l IO_L25P_4
+V15 io line r IO_L22N_4/VREF_4/400NC
+V16 io line l IO_L16N_4
+V17 io line l IO_L10N_4
+V18 io line r IO/VREF_4
W13 io line l IO
W14 io line l IO
-W15 io line r IO\_L22P\_4/400NC
-W16 io line l IO\_L16P\_4
-W17 io line l IO\_L10P\_4
-Y13 io line l IO\_L29N\_4
-Y17 io line l IO\_L15N\_4
-Y18 io line l IO\_L06P\_4
-AA13 io line l IO\_L29P\_4
-AA15 io line l IO\_L24N\_4
-AA16 io line r IO\_L19N\_4/400NC
-AA17 io line l IO\_L15P\_4
-AA18 io line l IO\_L09N\_4
-AA19 io line r IO\_L05N\_4/400NC
-AA20 io line l IO\_L01N\_4/VRP\_4/DCI
-AB15 io line l IO\_L24P\_4
-AB16 io line r IO\_L19P\_4/400NC
-AB18 io line l IO\_L09P\_4
-AB19 io line r IO\_L05P\_4/400NC
-AB20 io line l IO\_L01P\_4/VRN\_4/DCI
+W15 io line r IO_L22P_4/400NC
+W16 io line l IO_L16P_4
+W17 io line l IO_L10P_4
+W18 io line r IO_L06N_4/VREF_4
+Y13 io line l IO_L29N_4
+Y15 pwr line b VCCO_4
+Y16 io line r IO/VREF_4
+Y17 io line l IO_L15N_4
+Y18 io line l IO_L06P_4
+AA13 io line l IO_L29P_4
+AA15 io line l IO_L24N_4
+AA16 io line r IO_L19N_4/400NC
+AA17 io line l IO_L15P_4
+AA18 io line l IO_L09N_4
+AA19 io line r IO_L05N_4/400NC
+AA20 io line l IO_L01N_4/VRP_4/DCI
+AB13 io line r IO/VREF_4
+AB15 io line l IO_L24P_4
+AB16 io line r IO_L19P_4/400NC
+AB18 io line l IO_L09P_4
+AB19 io line r IO_L05P_4/400NC
+AB20 io line l IO_L01P_4/VRN_4/DCI
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO5.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,30 +18,40 @@
author=xilinxgen.py
numslots=0
[pins]
+T9 pwr line b VCCO_5
+T10 pwr line b VCCO_5
+T11 pwr line b VCCO_5
+U6 io line r IO/VREF_5
U7 io line l IO
+U8 pwr line b VCCO_5
U9 io line r IO/400NC
U10 io line l IO
U11 io line l IO
-V6 io line l IO\_L15P\_5
+V6 io line l IO_L15P_5
V7 io line l IO
-V8 io line l IO\_L24P\_5
-V9 io line l IO\_L27P\_5
+V8 io line l IO_L24P_5
+V9 io line l IO_L27P_5
V10 io line l IO
-W5 io line l IO\_L09P\_5
-W6 io line l IO\_L15N\_5
-W8 io line l IO\_L24N\_5
-Y5 io line l IO\_L09N\_5
-Y6 io line l IO\_L16P\_5
-Y7 io line r IO\_L19N\_5/400NC
-Y10 io line l IO\_L29N\_5
-AA4 io line l IO\_L06P\_5
-AA5 io line l IO\_L10P\_5/VRN\_5/DCI
-AA6 io line l IO\_L16N\_5
-AA7 io line r IO\_L22P\_5/400NC
-AA8 io line l IO\_L25P\_5
-AA10 io line l IO\_L30P\_5
-AB4 io line l IO\_L06N\_5
-AB5 io line l IO\_L10N\_5/VRP\_5/DCI
-AB7 io line r IO\_L22N\_5/400NC
-AB8 io line l IO\_L25N\_5
-AB10 io line l IO\_L30N\_5
+W5 io line l IO_L09P_5
+W6 io line l IO_L15N_5
+W7 io line r IO_L19P_5/VREF_5/400NC
+W8 io line l IO_L24N_5
+W9 io line r IO_L27N_5/VREF_5
+W10 io line r IO_L29P_5/VREF_5
+Y5 io line l IO_L09N_5
+Y6 io line l IO_L16P_5
+Y7 io line r IO_L19N_5/400NC
+Y8 pwr line b VCCO_5
+Y10 io line l IO_L29N_5
+AA4 io line l IO_L06P_5
+AA5 io line l IO_L10P_5/VRN_5/DCI
+AA6 io line l IO_L16N_5
+AA7 io line r IO_L22P_5/400NC
+AA8 io line l IO_L25P_5
+AA10 io line l IO_L30P_5
+AB4 io line l IO_L06N_5
+AB5 io line l IO_L10N_5/VRP_5/DCI
+AB7 io line r IO_L22N_5/400NC
+AB8 io line l IO_L25N_5
+AB10 io line l IO_L30N_5
+AB11 io line r IO/VREF_5
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO6.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,42 +18,51 @@
author=xilinxgen.py
numslots=0
[pins]
-M2 io line l IO\_L40N\_6
-M3 io line l IO\_L39P\_6
-M4 io line l IO\_L39N\_6
-M5 io line l IO\_L38P\_6
-M6 io line l IO\_L38N\_6
-N1 io line l IO\_L35P\_6
-N2 io line l IO\_L35N\_6
-N3 io line l IO\_L34P\_6
-N5 io line r IO\_L33P\_6/400NC
-N6 io line r IO\_L33N\_6/400NC
-P1 io line r IO\_L32P\_6/400NC
-P2 io line r IO\_L32N\_6/400NC
-P4 io line r IO\_L31P\_6/400NC
-P5 io line r IO\_L31N\_6/400NC
-P6 io line r IO\_L28P\_6/400NC
-R1 io line r IO\_L29P\_6/400NC
-R2 io line r IO\_L29N\_6/400NC
-R4 io line r IO\_L26P\_6/400NC
-R5 io line r IO\_L28N\_6/400NC
-T1 io line l IO\_L27P\_6
-T2 io line l IO\_L27N\_6
-T3 io line r IO\_L26N\_6/400NC
-T4 io line l IO\_L23P\_6
-T5 io line l IO\_L22P\_6
-T6 io line l IO\_L22N\_6
-U2 io line l IO\_L24P\_6
-U4 io line l IO\_L23N\_6
-U5 io line l IO\_L19P\_6
-V1 io line l IO\_L21P\_6
-V2 io line l IO\_L21N\_6
-V3 io line l IO\_L20P\_6
-V4 io line l IO\_L20N\_6
-V5 io line l IO\_L19N\_6
-W2 io line l IO\_L17N\_6
-W3 io line l IO\_L16P\_6
-W4 io line l IO\_L16N\_6
+M1 io line r IO_L40P_6/VREF_6
+M2 io line l IO_L40N_6
+M3 io line l IO_L39P_6
+M4 io line l IO_L39N_6
+M5 io line l IO_L38P_6
+M6 io line l IO_L38N_6
+M7 pwr line b VCCO_6
+N1 io line l IO_L35P_6
+N2 io line l IO_L35N_6
+N3 io line l IO_L34P_6
+N4 io line r IO_L34N_6/VREF_6
+N5 io line r IO_L33P_6/400NC
+N6 io line r IO_L33N_6/400NC
+N7 pwr line b VCCO_6
+P1 io line r IO_L32P_6/400NC
+P2 io line r IO_L32N_6/400NC
+P4 io line r IO_L31P_6/400NC
+P5 io line r IO_L31N_6/400NC
+P6 io line r IO_L28P_6/400NC
+P7 pwr line b VCCO_6
+R1 io line r IO_L29P_6/400NC
+R2 io line r IO_L29N_6/400NC
+R3 pwr line b VCCO_6
+R4 io line r IO_L26P_6/400NC
+R5 io line r IO_L28N_6/400NC
+R6 pwr line b VCCO_6
+T1 io line l IO_L27P_6
+T2 io line l IO_L27N_6
+T3 io line r IO_L26N_6/400NC
+T4 io line l IO_L23P_6
+T5 io line l IO_L22P_6
+T6 io line l IO_L22N_6
+U2 io line l IO_L24P_6
+U3 io line r IO_L24N_6/VREF_6
+U4 io line l IO_L23N_6
+U5 io line l IO_L19P_6
+V1 io line l IO_L21P_6
+V2 io line l IO_L21N_6
+V3 io line l IO_L20P_6
+V4 io line l IO_L20N_6
+V5 io line l IO_L19N_6
+W1 io line r IO_L17P_6/VREF_6
+W2 io line l IO_L17N_6
+W3 io line l IO_L16P_6
+W4 io line l IO_L16N_6
Y1 io line l IO
-Y2 io line l IO\_L01P\_6/VRN\_6/DCI
-Y3 io line l IO\_L01N\_6/VRP\_6/DCI
+Y2 io line l IO_L01P_6/VRN_6/DCI
+Y3 io line l IO_L01N_6/VRP_6/DCI
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-IO7.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -18,42 +18,51 @@
author=xilinxgen.py
numslots=0
[pins]
+C1 io line r IO_L16P_7/VREF_7
C2 io line l IO
-C3 io line l IO\_L01N\_7/VRP\_7/DCI
-C4 io line l IO\_L01P\_7/VRN\_7/DCI
-D1 io line l IO\_L16N\_7
-D2 io line l IO\_L19P\_7
-D4 io line l IO\_L17P\_7
-E1 io line l IO\_L21N\_7
-E2 io line l IO\_L21P\_7
-E3 io line l IO\_L20P\_7
-E4 io line l IO\_L17N\_7
-F2 io line l IO\_L23N\_7
-F3 io line l IO\_L23P\_7
-F4 io line l IO\_L20N\_7
-F5 io line l IO\_L22P\_7
-G1 io line l IO\_L27N\_7
-G3 io line r IO\_L26N\_7/400NC
-G4 io line r IO\_L26P\_7/400NC
-G5 io line l IO\_L24P\_7
-G6 io line l IO\_L22N\_7
-H1 io line r IO\_L28N\_7/400NC
-H2 io line r IO\_L28P\_7/400NC
-H4 io line r IO\_L29P\_7/400NC
-H5 io line l IO\_L24N\_7
-J1 io line r IO\_L32N\_7/400NC
-J2 io line r IO\_L32P\_7/400NC
-J4 io line r IO\_L29N\_7/400NC
-J5 io line r IO\_L31N\_7/400NC
-J6 io line r IO\_L31P\_7/400NC
-K1 io line l IO\_L35N\_7
-K2 io line l IO\_L35P\_7
-K3 io line l IO\_L34N\_7
-K4 io line l IO\_L34P\_7
-K5 io line r IO\_L33N\_7/400NC
-K6 io line r IO\_L33P\_7/400NC
-L2 io line l IO\_L40P\_7
-L3 io line l IO\_L39N\_7
-L4 io line l IO\_L39P\_7
-L5 io line l IO\_L38N\_7
-L6 io line l IO\_L38P\_7
+C3 io line l IO_L01N_7/VRP_7/DCI
+C4 io line l IO_L01P_7/VRN_7/DCI
+D1 io line l IO_L16N_7
+D2 io line l IO_L19P_7
+D3 io line r IO_L19N_7/VREF_7
+D4 io line l IO_L17P_7
+E1 io line l IO_L21N_7
+E2 io line l IO_L21P_7
+E3 io line l IO_L20P_7
+E4 io line l IO_L17N_7
+F2 io line l IO_L23N_7
+F3 io line l IO_L23P_7
+F4 io line l IO_L20N_7
+F5 io line l IO_L22P_7
+G1 io line l IO_L27N_7
+G2 io line r IO_L27P_7/VREF_7
+G3 io line r IO_L26N_7/400NC
+G4 io line r IO_L26P_7/400NC
+G5 io line l IO_L24P_7
+G6 io line l IO_L22N_7
+H1 io line r IO_L28N_7/400NC
+H2 io line r IO_L28P_7/400NC
+H3 pwr line b VCCO_7
+H4 io line r IO_L29P_7/400NC
+H5 io line l IO_L24N_7
+H6 pwr line b VCCO_7
+J1 io line r IO_L32N_7/400NC
+J2 io line r IO_L32P_7/400NC
+J4 io line r IO_L29N_7/400NC
+J5 io line r IO_L31N_7/400NC
+J6 io line r IO_L31P_7/400NC
+J7 pwr line b VCCO_7
+K1 io line l IO_L35N_7
+K2 io line l IO_L35P_7
+K3 io line l IO_L34N_7
+K4 io line l IO_L34P_7
+K5 io line r IO_L33N_7/400NC
+K6 io line r IO_L33P_7/400NC
+K7 pwr line b VCCO_7
+L1 io line r IO_L40N_7/VREF_7
+L2 io line l IO_L40P_7
+L3 io line l IO_L39N_7
+L4 io line l IO_L39P_7
+L5 io line l IO_L38N_7
+L6 io line l IO_L38P_7
+L7 pwr line b VCCO_7
Modified: usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src 2006-10-16 02:54:58 UTC
(rev 3794)
+++ usrp-hw/trunk/sym/generated/xc3sXX00fg456-PWR.src 2006-10-16 03:54:40 UTC
(rev 3795)
@@ -24,106 +24,66 @@
A22 pwr line r GND
B2 pwr line r GND
B21 pwr line r GND
-C8 pwr line l VCCO\_0
C9 pwr line r GND
C14 pwr line r GND
-C15 pwr line l VCCO\_1
F1 pwr line l VCCAUX
-F8 pwr line l VCCO\_0
-F15 pwr line l VCCO\_1
F22 pwr line l VCCAUX
G7 pwr line l VCCINT
G8 pwr line l VCCINT
-G9 pwr line l VCCO\_0
-G10 pwr line l VCCO\_0
-G11 pwr line l VCCO\_0
-G12 pwr line l VCCO\_1
-G13 pwr line l VCCO\_1
-G14 pwr line l VCCO\_1
G15 pwr line l VCCINT
G16 pwr line l VCCINT
-H3 pwr line l VCCO\_7
-H6 pwr line l VCCO\_7
H7 pwr line l VCCINT
H16 pwr line l VCCINT
-H17 pwr line l VCCO\_2
-H20 pwr line l VCCO\_2
J3 pwr line r GND
-J7 pwr line l VCCO\_7
J9 pwr line r GND
J10 pwr line r GND
J11 pwr line r GND
J12 pwr line r GND
J13 pwr line r GND
J14 pwr line r GND
-J16 pwr line l VCCO\_2
J20 pwr line r GND
-K7 pwr line l VCCO\_7
K9 pwr line r GND
K10 pwr line r GND
K11 pwr line r GND
K12 pwr line r GND
K13 pwr line r GND
K14 pwr line r GND
-K16 pwr line l VCCO\_2
-L7 pwr line l VCCO\_7
L9 pwr line r GND
L10 pwr line r GND
L11 pwr line r GND
L12 pwr line r GND
L13 pwr line r GND
L14 pwr line r GND
-L16 pwr line l VCCO\_2
-M7 pwr line l VCCO\_6
M9 pwr line r GND
M10 pwr line r GND
M11 pwr line r GND
M12 pwr line r GND
M13 pwr line r GND
M14 pwr line r GND
-M16 pwr line l VCCO\_3
-N7 pwr line l VCCO\_6
N9 pwr line r GND
N10 pwr line r GND
N11 pwr line r GND
N12 pwr line r GND
N13 pwr line r GND
N14 pwr line r GND
-N16 pwr line l VCCO\_3
P3 pwr line r GND
-P7 pwr line l VCCO\_6
P9 pwr line r GND
P10 pwr line r GND
P11 pwr line r GND
P12 pwr line r GND
P13 pwr line r GND
P14 pwr line r GND
-P16 pwr line l VCCO\_3
P20 pwr line r GND
-R3 pwr line l VCCO\_6
-R6 pwr line l VCCO\_6
R7 pwr line l VCCINT
R16 pwr line l VCCINT
-R17 pwr line l VCCO\_3
-R20 pwr line l VCCO\_3
T7 pwr line l VCCINT
T8 pwr line l VCCINT
-T9 pwr line l VCCO\_5
-T10 pwr line l VCCO\_5
-T11 pwr line l VCCO\_5
-T12 pwr line l VCCO\_4
-T13 pwr line l VCCO\_4
-T14 pwr line l VCCO\_4
T15 pwr line l VCCINT
T16 pwr line l VCCINT
U1 pwr line l VCCAUX
-U8 pwr line l VCCO\_5
-U15 pwr line l VCCO\_4
U22 pwr line l VCCAUX
-Y8 pwr line l VCCO\_5
Y9 pwr line r GND
Y14 pwr line r GND
-Y15 pwr line l VCCO\_4
AA2 pwr line r GND
AA21 pwr line r GND
AB1 pwr line r GND
Deleted: usrp-hw/trunk/sym/generated/xc3sXX00fg456-VREF.src
Deleted: usrp-hw/trunk/sym/generated/xilinxgen
Added: usrp-hw/trunk/sym/generated/xilinxgen320
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen320 (rev 0)
+++ usrp-hw/trunk/sym/generated/xilinxgen320 2006-10-16 03:54:40 UTC (rev
3795)
@@ -0,0 +1,106 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ #file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" % (number,pintype,linetype,pos,name))
+
+pinfile = open ('fg320_table.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG320-%s
+device=XC3SXX00FG320
+refdes=U?
+footprint=FG320
+description=Xilinx Spartan 3 400/1000/1500 FG320
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3sXX00fg320-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3sXX00fg320-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3sXX00fg320-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+clockfile = open ('xc3sXX00fg320-CLK.src', 'w')
+clockfile.write(boilerplate % ("CLK",))
+
+iofiles = [0] * 8
+for i in range(8):
+ iofiles[i] = open ( ('xc3sXX00fg320-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[6]
+ nc = elements[4] == "N.C."
+
+ if(elements[4] != elements[8]) and not nc:
+ print "error"
+ print elements
+
+ if nc and pintype != 'I/O' and pintype != 'VREF':
+ print "error"
+ print elements
+
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[2],elements[5],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[2],elements[5],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[2],elements[5],'line','pwr','l')
+
writepin(iofiles[int(elements[9])],elements[2],elements[5],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[2],elements[5],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[2],elements[5],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ writepin(configfile,elements[2],elements[5],'line','io','l')
+
+ elif(pintype == 'DUAL'):
+ writepin(configfile,elements[2],elements[5],'line','io','r')
+
+ elif(pintype == 'GCLK'):
+ writepin(clockfile,elements[2],elements[5],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+ if nc:
+ writepin(iofiles[int(elements[9])],elements[2],"%s/400NC" %
(elements[5],),'line','io','r')
+ else:
+
writepin(iofiles[int(elements[9])],elements[2],elements[5],'line','io','r')
+
+ elif(pintype == 'I/O'):
+ if nc:
+ writepin(iofiles[int(elements[9])],elements[2],"%s/400NC" %
(elements[5],),'line','io','r')
+ else:
+
writepin(iofiles[int(elements[9])],elements[2],elements[5],'line','io','l')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[9])],elements[2],"%s/DCI" %
(elements[5],),'line','io','l')
+
+ else:
+ print elements
Property changes on: usrp-hw/trunk/sym/generated/xilinxgen320
___________________________________________________________________
Name: svn:executable
+ *
Copied: usrp-hw/trunk/sym/generated/xilinxgen456 (from rev 3789,
usrp-hw/trunk/sym/generated/xilinxgen)
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen456 (rev 0)
+++ usrp-hw/trunk/sym/generated/xilinxgen456 2006-10-16 03:54:40 UTC (rev
3795)
@@ -0,0 +1,106 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ newname = name
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('fg456_table.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-%s
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3sXX00fg456-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3sXX00fg456-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3sXX00fg456-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+clockfile = open ('xc3sXX00fg456-CLK.src', 'w')
+clockfile.write(boilerplate % ("CLK",))
+
+iofiles = [0] * 8
+for i in range(8):
+ iofiles[i] = open ( ('xc3sXX00fg456-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[7]
+ nc = elements[5] == "N.C."
+
+ if(elements[5] != elements[9]) and not nc:
+ print "error"
+ print elements
+
+ if nc and pintype != 'I/O' and pintype != 'VREF':
+ print "error"
+ print elements
+
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[3],elements[6],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
writepin(iofiles[int(elements[12])],elements[3],elements[6],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[3],elements[6],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ writepin(configfile,elements[3],elements[6],'line','io','l')
+
+ elif(pintype == 'DUAL'):
+ writepin(configfile,elements[3],elements[6],'line','io','r')
+
+ elif(pintype == 'GCLK'):
+ writepin(clockfile,elements[3],elements[6],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+ if nc:
+ writepin(iofiles[int(elements[12])],elements[3],"%s/400NC" %
(elements[6],),'line','io','r')
+ else:
+
writepin(iofiles[int(elements[12])],elements[3],elements[6],'line','io','r')
+
+ elif(pintype == 'I/O'):
+ if nc:
+ writepin(iofiles[int(elements[12])],elements[3],"%s/400NC" %
(elements[6],),'line','io','r')
+ else:
+
writepin(iofiles[int(elements[12])],elements[3],elements[6],'line','io','l')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" %
(elements[6],),'line','io','l')
+
+ else:
+ print elements
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- [Commit-gnuradio] r3795 - usrp-hw/trunk/sym/generated,
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