[Commit-gnuradio] r4831 - gnuradio/branches/developers/matt/u2f/boot_cpld

[matt]

Author: matt
Date: 2007-03-31 13:50:27 -0600 (Sat, 31 Mar 2007)
New Revision: 4831

Modified:
   gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
Log:
basic heartbeat


Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-03-31 
19:42:54 UTC (rev 4830)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-03-31 
19:50:27 UTC (rev 4831)
@@ -18,28 +18,45 @@
 // Additional Comments: 
 //
 
//////////////////////////////////////////////////////////////////////////////////
-module boot_cpld(CLK_25MHZ, CLK_25MHZ_EN, LED, SPI_CPLD_CLK, SPI_CPLD_DIN, 
SPI_CPLD_DOUT, SPI_CPLD_EN, SD_nCS, SD_Din, SD_CLK, SD_Dout, SD_DAT1, SD_DAT2, 
CFG_INIT_B, CFG_Din, DEBUG, POR, CFG_CCLK, CFG_DONE, CFG_PROG_B);
-    input CLK_25MHZ;
-    output CLK_25MHZ_EN;
-    output [2:0] LED;
-    input SPI_CPLD_CLK;
-    input SPI_CPLD_DIN;
-    input SPI_CPLD_DOUT;
-    input SPI_CPLD_EN;
-    output SD_nCS;
-    output SD_Din;
-    output SD_CLK;
-    input SD_Dout;
-    input SD_DAT1;
-    input SD_DAT2;
-    input CFG_INIT_B;
-    input CFG_Din;
-    output [10:0] DEBUG;
-    input POR;
-    input CFG_CCLK;
-    input CFG_DONE;
-    input CFG_PROG_B;
+module boot_cpld
+  (CLK_25MHZ, CLK_25MHZ_EN, LED, SPI_CPLD_CLK, SPI_CPLD_DIN, SPI_CPLD_DOUT, 
SPI_CPLD_EN, 
+   SD_nCS, SD_Din, SD_CLK, SD_Dout, SD_DAT1, SD_DAT2, CFG_INIT_B, CFG_Din, 
DEBUG, POR, 
+   CFG_CCLK, CFG_DONE, CFG_PROG_B);
+   
+   input CLK_25MHZ;
+   output CLK_25MHZ_EN;
+   output [2:0] LED;
+   input       SPI_CPLD_CLK;
+   input       SPI_CPLD_DIN;
+   input       SPI_CPLD_DOUT;
+   input       SPI_CPLD_EN;
+   output      SD_nCS;
+   output      SD_Din;
+   output      SD_CLK;
+   input       SD_Dout;
+   input       SD_DAT1;
+   input       SD_DAT2;
+   input       CFG_INIT_B;
+   input       CFG_Din;
+   output [10:0] DEBUG;
+   input        POR;
+   input        CFG_CCLK;
+   input        CFG_DONE;
+   input        CFG_PROG_B;
 
+   assign       CLK_25MHZ_EN = 1'b1;
 
+   reg [23:0]   counter;
 
-endmodule
+   always @(posedge CLK_25MHZ)
+     counter <= #1 counter + 24'd1;
+
+   assign       LED[0] = 1'b1;
+   assign       LED[1] = 1'b0;
+   assign       LED[2] = counter[23];
+
+   assign       DEBUG = counter[23:13];
+   
+
+endmodule // boot_cpld
+