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[Commit-gnuradio] r4878 - gnuradio/branches/developers/jcorgan/sar-fe/gr
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From: |
jcorgan |
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Subject: |
[Commit-gnuradio] r4878 - gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel |
|
Date: |
Wed, 4 Apr 2007 20:31:21 -0600 (MDT) |
Author: jcorgan
Date: 2007-04-04 20:31:21 -0600 (Wed, 04 Apr 2007)
New Revision: 4878
Removed:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
Log:
Receiver/transmitter-ectomy.
Deleted:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-04-04 20:11:52 UTC (rev 4877)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
2007-04-05 02:31:21 UTC (rev 4878)
@@ -368,41 +368,18 @@
# end ENTITY(usrp_sar)
# --------------------
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/hb/coeff_ram.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/adc_interface.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/megacells/bustri.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE usrp_sar.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/sign_extend.v
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE usrp_sar.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-04-04 20:11:52 UTC (rev 4877)
+++
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
2007-04-05 02:31:21 UTC (rev 4878)
@@ -3,6 +3,7 @@
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
+// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -19,15 +20,6 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-// Top level module for a full setup with DUCs and DDCs
-
-// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
-// for debugging info. NB, This can kill the m'board and/or d'board if you
-// have anything except basic d'boards installed.
-
-// Uncomment the following to include optional circuitry
-
-`include "config.vh"
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
@@ -43,14 +35,15 @@
output FX2_2,
output FX2_3,
+ // ADC bus
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
+ // DAC bus
output wire [13:0] tx_a,
output wire [13:0] tx_b,
-
output wire TXSYNC_A,
output wire TXSYNC_B,
@@ -71,12 +64,12 @@
wire clk64,clk128;
- wire WR = usbctl[0];
+ wire WR = usbctl[0]; // Not used
wire RD = usbctl[1];
wire OE = usbctl[2];
- wire have_space, have_pkt_rdy;
- assign usbrdy[0] = have_space;
+ wire have_pkt_rdy;
+ assign usbrdy[0] = 1'b0; // have_space;
assign usbrdy[1] = have_pkt_rdy;
wire tx_underrun, rx_overrun;
@@ -97,7 +90,6 @@
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
- wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
@@ -120,189 +112,74 @@
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
-`ifdef TX_ON
- assign bb_tx_i0 = ch0tx;
- assign bb_tx_q0 = ch1tx;
- assign bb_tx_i1 = ch2tx;
- assign bb_tx_q1 = ch3tx;
-
- tx_buffer tx_buffer
- ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
-
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
- .channels({tx_numchan,1'b0}),
- .tx_i_0(ch0tx),.tx_q_0(ch1tx),
- .tx_i_1(ch2tx),.tx_q_1(ch3tx),
- .tx_i_2(),.tx_q_2(),
- .tx_i_3(),.tx_q_3(),
- .txclk(clk64),.txstrobe(strobe_interp),
- .clear_status(clear_status),
- .tx_empty(tx_empty),
- .debugbus(tx_debugbus) );
- `ifdef TX_EN_0
- tx_chain tx_chain_0
- ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
- .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
- .interpolator_strobe(strobe_interp),.freq(),
- .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
- `else
- assign i_out_0=16'd0;
- assign q_out_0=16'd0;
- `endif
+ wire [15:0] tx_i;
+ wire [15:0] tx_q;
- `ifdef TX_EN_1
- tx_chain tx_chain_1
- ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
- .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
- .interpolator_strobe(strobe_interp),.freq(),
- .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
- `else
- assign i_out_1=16'd0;
- assign q_out_1=16'd0;
- `endif
-
- setting_reg #(`FR_TX_MUX)
-
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
-
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
-
- wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 :
i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
- wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 :
i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
- wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 :
i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
- wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 :
i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
-
wire txsync = tx_sample_strobe;
+ assign tx_a = txsync ? tx_i[15:2] : tx_q[15:2];
+ assign tx_b = 14'b0;
assign TXSYNC_A = txsync;
assign TXSYNC_B = txsync;
- assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
- assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
-`endif // `ifdef TX_ON
-
+ // Put sar_tx block here that drives tx_i, tx_q, txsync
+ assign tx_i = 16'b0;
+ assign tx_q = 16'b0;
+
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
-`ifdef RX_ON
- wire rx_sample_strobe,strobe_decim,hb_strobe;
- wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
- bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
- wire loopback = settings[0];
- wire counter = settings[1];
+ wire [31:0] rssi_i,rssi_q;
+ wire [15:0] rx_in_i,rx_in_q;
- always @(posedge clk64)
- if(rx_dsp_reset)
- debug_counter <= #1 16'd0;
- else if(~enable_rx)
- debug_counter <= #1 16'd0;
- else if(hb_strobe)
- debug_counter <=#1 debug_counter + 16'd2;
-
- always @(posedge clk64)
- if(strobe_interp)
- begin
- loopback_i_0 <= #1 ch0tx;
- loopback_q_0 <= #1 ch1tx;
- end
-
- assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
- assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 :
bb_rx_q0;
- assign ch2rx = bb_rx_i1;
- assign ch3rx = bb_rx_q1;
- assign ch4rx = bb_rx_i2;
- assign ch5rx = bb_rx_q2;
- assign ch6rx = bb_rx_i3;
- assign ch7rx = bb_rx_q3;
-
- wire [15:0]
ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
- wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
-
adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
-
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
- .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
- .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
- .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
-
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
-
+
.rssi_0(rssi_i),.rssi_1(rssi_q),.rssi_2(),.rssi_3(),
+ .ddc0_in_i(rx_in_i),.ddc0_in_q(rx_in_q),
+ .ddc1_in_i(),.ddc1_in_q(),
+ .ddc2_in_i(),.ddc2_in_q(),
+
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan));
+
+
+ // Put sar_rx block here, reading rx_in_i, rx_in_q, and driving rx_i, rx_q,
rx_strobe
+ wire [15:0] rx_i, rx_q;
+ wire rx_strobe;
+
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
- .ch_0(ch0rx),.ch_1(ch1rx),
- .ch_2(ch2rx),.ch_3(ch3rx),
- .ch_4(ch4rx),.ch_5(ch5rx),
- .ch_6(ch6rx),.ch_7(ch7rx),
- .rxclk(clk64),.rxstrobe(hb_strobe),
+ .ch_0(rx_i),.ch_1(rx_q),
+ .ch_2(),.ch_3(),
+ .ch_4(),.ch_5(),
+ .ch_6(),.ch_7(),
+ .rxclk(clk64),.rxstrobe(rx_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .debugbus(rx_debugbus) );
-
- `ifdef RX_EN_0
- rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
- ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
-
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
- `else
- assign bb_rx_i0=16'd0;
- assign bb_rx_q0=16'd0;
- `endif
-
- `ifdef RX_EN_1
- rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
- ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
-
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
- `else
- assign bb_rx_i1=16'd0;
- assign bb_rx_q1=16'd0;
- `endif
-
- `ifdef RX_EN_2
- rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
- ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
-
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
- `else
- assign bb_rx_i2=16'd0;
- assign bb_rx_q2=16'd0;
- `endif
+ .debugbus(rx_debugbus));
- `ifdef RX_EN_3
- rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
- ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
-
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
- `else
- assign bb_rx_i3=16'd0;
- assign bb_rx_q3=16'd0;
- `endif
-`endif // `ifdef RX_ON
-
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
- assign capabilities[7] = `TX_CAP_HB;
- assign capabilities[6:4] = `TX_CAP_NCHAN;
- assign capabilities[3] = `RX_CAP_HB;
- assign capabilities[2:0] = `RX_CAP_NCHAN;
+ assign capabilities[7] = 1'b0; // `TX_CAP_HB;
+ assign capabilities[6:4] = 3'b0; // `TX_CAP_NCHAN;
+ assign capabilities[3] = 1'b0; // `RX_CAP_HB;
+ assign capabilities[2:0] = 3'd2; // `RX_CAP_NCHAN;
-
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
-
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
+ .readback_4(rssi_i),.readback_5(rssi_q),.readback_6(),.readback_7()
);
wire [15:0] reg_0,reg_1,reg_2,reg_3;
@@ -316,8 +193,7 @@
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
- //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_0(),.debug_1(),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
@@ -327,8 +203,4 @@
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
-
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // Misc Settings
- setting_reg #(`FR_MODE)
sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
-
endmodule // usrp_sar
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- [Commit-gnuradio] r4878 - gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel,
jcorgan <=