[Commit-gnuradio] r4921 - gnuradio/branches/developers/matt/u2f/top/safe_bringup

[matt]

Author: matt
Date: 2007-04-07 17:36:19 -0600 (Sat, 07 Apr 2007)
New Revision: 4921

Modified:
   gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
Log:
nearly everything in safe mode, now turns on main clk


Modified: gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v       
2007-04-07 23:34:53 UTC (rev 4920)
+++ gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v       
2007-04-07 23:36:19 UTC (rev 4921)
@@ -1,26 +1,18 @@
 `timescale 1ns / 1ps
 
//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    16:40:10 03/28/2007 
-// Design Name: 
-// Module Name:    u2_basic 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
+// Module Name:    safe_bringup
 //
-// Dependencies: 
-//
 // Revision: 
 // Revision 0.01 - File Created
 // Additional Comments: 
 //
 
//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
 module safe_bringup
   (
-
+ 
    // Misc, debug
    output led1,
    output led2,
@@ -29,7 +21,7 @@
 
    // Expansion
    input exp_pps_in, // Diff
-   output exp_pps_out, // Diff 
+   input exp_pps_out, // Diff 
    
    // GMII
    //   GMII-CTRL
@@ -37,11 +29,11 @@
    input GMII_CRS,
 
    //   GMII-TX
-   output [7:0] GMII_TXD,
-   output GMII_TX_EN,
-   output GMII_TX_ER,
-   output GMII_GTX_CLK,
-   output GMII_TX_CLK,  // 100mbps clk
+   input [7:0] GMII_TXD,
+   input GMII_TX_EN,
+   input GMII_TX_ER,
+   input GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
 
    //   GMII-RX
    input [7:0] GMII_RXD,
@@ -50,70 +42,70 @@
    input GMII_RX_ER,
 
    //   GMII-Management
-   inout MDIO,
-   output MDC,
+   input MDIO,
+   input MDC,
    input PHY_INTn,   // open drain
-   output PHY_RESETn,
-   output PHY_CLK,   // possibly use on-board osc
+   input PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
 
    // RAM
-   inout [17:0] RAM_D,
-   output [18:0] RAM_A,
-   output RAM_CE1n,
-   output RAM_CENn,
-   output RAM_CLK,
-   output RAM_WEn,
-   output RAM_OEn,
-   output RAM_LDn,
+   input [17:0] RAM_D,
+   input [18:0] RAM_A,
+   input RAM_CE1n,
+   input RAM_CENn,
+   input RAM_CLK,
+   input RAM_WEn,
+   input RAM_OEn,
+   input RAM_LDn,
    
    // SERDES
-   output ser_enable,
-   output ser_prbsen,
-   output ser_loopen,
+   input ser_enable,
+   input ser_prbsen,
+   input ser_loopen,
    
-   output ser_tx_clk,
-   output [15:0] ser_t,
-   output ser_tklsb,
-   output ser_tkmsb,
+   input ser_tx_clk,
+   input [15:0] ser_t,
+   input ser_tklsb,
+   input ser_tkmsb,
 
    input ser_rx_clk,
-   output ser_rx_en,
+   input ser_rx_en,
    input [15:0] ser_r,
    input ser_rklsb,
    input ser_rkmsb,
    
    // CPLD interface
-   output spi_cpld_en,
-   output spi_cpld_dout,
+   input spi_cpld_en,
+   input spi_cpld_dout,
    input spi_cpld_din,
    input spi_cpld_clk,   // temporary bootstrap clock
    
    // ADC
    input [13:0] adc_a,
    input adc_ovf_a,
-   output adc_oen_a,
-   output adc_pdn_a,
+   input adc_oen_a,
+   input adc_pdn_a,
    
    input [13:0] adc_b,
    input adc_ovf_b,
-   output adc_oen_b,
-   output adc_pdn_b,
+   input adc_oen_b,
+   input adc_pdn_b,
    
    // DAC
-   output [15:0] dac_a,
-   output [15:0] dac_b,
+   input [15:0] dac_a,
+   input [15:0] dac_b,
 
    
    // I2C
-   inout SCL,
-   inout SDA,
-   output SCL_force,
-   output SDA_force,
+   input SCL,
+   input SDA,
+   input SCL_force,
+   input SDA_force,
 
    // Clock Gen Control
    output [1:0] clk_en,
    output [1:0] clk_sel,
-   input clk_func,        // FIXME is an output to control the 9510
+   input clk_func,        // FIXME is an input to control the 9510
    input clk_status,
 
    // Clocks
@@ -124,49 +116,67 @@
    // Generic SPI
    output sclk,
    output sen_clk,
-   output sen_dac,
+   input sen_dac,
    output sdi,
    input sdo,
    
    // TX DBoard
-   output sen_tx_db,
-   output sclk_tx_db,
-   output sdo_tx_db,
+   input sen_tx_db,
+   input sclk_tx_db,
+   input sdo_tx_db,
    input sdi_tx_db,
 
-   output sen_tx_adc,
-   output sclk_tx_adc,
-   output sdo_tx_adc,
+   input sen_tx_adc,
+   input sclk_tx_adc,
+   input sdo_tx_adc,
    input sdi_tx_adc,
 
-   output sen_tx_dac,
-   output sclk_tx_dac,
-   output sdi_tx_dac,
+   input sen_tx_dac,
+   input sclk_tx_dac,
+   input sdi_tx_dac,
 
-   inout [15:0] io_tx,
+   input [15:0] io_tx,
 
    // RX DBoard
-   output sen_rx_db,
-   output sclk_rx_db,
-   output sdo_rx_db,
+   input sen_rx_db,
+   input sclk_rx_db,
+   input sdo_rx_db,
    input sdi_rx_db,
 
-   output sen_rx_adc,
-   output sclk_rx_adc,
-   output sdo_rx_adc,
+   input sen_rx_adc,
+   input sclk_rx_adc,
+   input sdo_rx_adc,
    input sdi_rx_adc,
 
-   output sen_rx_dac,
-   output sclk_rx_dac,
-   output sdi_rx_dac,
+   input sen_rx_dac,
+   input sclk_rx_dac,
+   input sdi_rx_dac,
 
-   inout [15:0] io_rx
+   input [15:0] io_rx
    );
+
+       wire reset;
+       reg [31:0] rst_ctr;
+       
+       wire    aux_clk = spi_cpld_clk;
+       assign reset = rst_ctr[29];
+       
+       always @(posedge aux_clk)
+               rst_ctr <= rst_ctr + 32'd1;
+               
+   
+   reg [23:0] counter;
+       always @(posedge aux_clk)
+               counter <= #1 counter + 24'd1;
 
-   wire        aux_clk = spi_cpld_clk;
+       assign debug = {rst_ctr[31:5], reset, sen_clk, sclk, sdi, sdo};
+       assign led1 = counter[23];
+       assign led2 = 1'b0;
+       assign debug_clk[0] = aux_clk;
+       assign debug_clk[1] = clk_fpga; 
    
    clock_control clock_control 
-     (.reset(),
+     (.reset(reset),
       .aux_clk(aux_clk),    // 25MHz, for before fpga clock is active
       .clk_fpga(clk_fpga),  // real 100 MHz FPGA clock
       .clk_en(clk_en),      // controls source of reference clock
@@ -175,8 +185,9 @@
       .clk_status(clk_status),  // Monitor PLL or SYNC status
       
       .sen(sen_clk),        // Enable for the AD9510
-      .sclk(sclk),.sdi(sdi),.sdo(sdo)  // FIXME these need to be shared
+      .sclk(sclk),.sdi(sdo),.sdo(sdi)  // FIXME these need to be shared
       );
-   
+  
+ 
 endmodule // u2_basic