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[Commit-gnuradio] r5103 - gnuradio/branches/developers/matt/u2f/top/u2_f
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5103 - gnuradio/branches/developers/matt/u2f/top/u2_fpga |
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Date: |
Wed, 25 Apr 2007 02:01:45 -0600 (MDT) |
Author: matt
Date: 2007-04-25 02:01:44 -0600 (Wed, 25 Apr 2007)
New Revision: 5103
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
everything connected now
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-04-25 07:59:47 UTC (rev 5102)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-04-25 08:01:44 UTC (rev 5103)
@@ -76,11 +76,12 @@
input ser_rkmsb,
// CPLD interface
- input spi_cpld_en,
- input spi_cpld_dout,
- input spi_cpld_din, // temporary POR
- input spi_cpld_clk, // temporary bootstrap clock
-
+ output cpld_start, // AA9
+ output cpld_mode, // U12
+ output cpld_done, // V12
+ input cpld_din, // AA14 Now shared with CFG_Din
+ input cpld_clk, // AB14 serial clock
+
// ADC
input [13:0] adc_a,
input adc_ovf_a,
@@ -96,7 +97,6 @@
output [15:0] dac_a,
output [15:0] dac_b,
-
// I2C
inout SCL,
inout SDA,
@@ -110,7 +110,7 @@
input clk_status,
// Clocks
- input clk_fpga_p,
+ input clk_fpga_p, // Diff
input clk_fpga_n, // Diff
input clk_to_mac,
input pps_in,
@@ -156,7 +156,8 @@
inout [15:0] io_rx
);
-
+
+ // FPGA-specific pins connections
wire clk_fpga;
IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
@@ -169,43 +170,31 @@
OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
- IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
- IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
// Don't use external transistors for open drain, the FPGA implements this
assign SCL_force = 1'b0;
assign SDA_force = 1'b0;
-
// LEDs are active low outputs
wire led1_int, led2_int;
assign led1 = ~led1_int;
assign led2 = ~led2_int;
-
- u2_basic u2_basic(/*AUTOINST*/
- // Outputs
+
+ wire aux_clk = RAM_CE1n; // FIXME Hacked on with Blue Wire
+ wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
+
+ u2_basic u2_basic(.clk_fpga (clk_fpga),
+ .aux_clk (aux_clk),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
.led1 (led1_int),
.led2 (led2_int),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
- .exp_pps_out (exp_pps_out),
- .adc_oen_a (adc_oen_a),
- .adc_pdn_a (adc_pdn_a),
- .adc_oen_b (adc_oen_b),
- .adc_pdn_b (adc_pdn_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .sclk (sclk),
- .sen_clk (sen_clk),
- .sdi (sdi),
- // Inputs
.exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
.GMII_COL (GMII_COL),
.GMII_CRS (GMII_CRS),
.GMII_TXD (GMII_TXD[7:0]),
@@ -222,44 +211,48 @@
.PHY_INTn (PHY_INTn),
.PHY_RESETn (PHY_RESETn),
.PHY_CLK (PHY_CLK),
- .RAM_D (RAM_D[17:0]),
- .RAM_A (RAM_A[18:0]),
- .RAM_CE1n (RAM_CE1n),
- .RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
- .RAM_WEn (RAM_WEn),
- .RAM_OEn (RAM_OEn),
- .RAM_LDn (RAM_LDn),
.ser_enable (ser_enable),
.ser_prbsen (ser_prbsen),
.ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
.ser_tx_clk (ser_tx_clk),
.ser_t (ser_t[15:0]),
.ser_tklsb (ser_tklsb),
.ser_tkmsb (ser_tkmsb),
.ser_rx_clk (ser_rx_clk),
- .ser_rx_en (ser_rx_en),
.ser_r (ser_r[15:0]),
.ser_rklsb (ser_rklsb),
.ser_rkmsb (ser_rkmsb),
- .spi_cpld_en (spi_cpld_en),
- .spi_cpld_dout (spi_cpld_dout),
- .POR (spi_cpld_din), // FIXME
- .aux_clk (spi_cpld_clk), // FIXME
- // .spi_cpld_din (spi_cpld_din), // FIXME
- // .spi_cpld_clk (spi_cpld_clk), // FIXME
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
.adc_a (adc_a[13:0]),
.adc_ovf_a (adc_ovf_a),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
.adc_b (adc_b[13:0]),
.adc_ovf_b (adc_ovf_b),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
.scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
.sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
.clk_func (clk_func),
.clk_status (clk_status),
- .clk_fpga (clk_fpga),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
+ .sclk (sclk),
+ .sen_clk (sen_clk),
.sen_dac (sen_dac),
+ .sdi (sdi),
.sdo (sdo),
.sen_tx_db (sen_tx_db),
.sclk_tx_db (sclk_tx_db),
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