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[Commit-gnuradio] r5667 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5667 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/sdr_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
|
Date: |
Mon, 4 Jun 2007 13:24:30 -0600 (MDT) |
Author: thottelt
Date: 2007-06-04 13:24:30 -0600 (Mon, 04 Jun 2007)
New Revision: 5667
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/master_control.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/rx_buffer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
fix sensitivity lists
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -39,8 +39,6 @@
/* State registers */
reg [3:0] reader_state;
- reg [3:0] reader_next_state;
-
reg [8:0] payload_len;
reg [8:0] read_len;
@@ -52,7 +50,6 @@
if (reset)
begin
reader_state <= `IDLE;
- reader_next_state <= `IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
@@ -63,14 +60,12 @@
end
else
begin
- reader_state = reader_next_state;
-
case (reader_state)
`IDLE:
begin
if (pkt_waiting == 1)
begin
- reader_next_state <= `READ;
+ reader_state <= `READ;
rdreq <= 1;
underrun <= 0;
end
@@ -84,7 +79,7 @@
/* Just wait for the fifodata to show up */
`READ:
begin
- reader_next_state <= `HEADER;
+ reader_state <= `HEADER;
if (tx_strobe)
tx_empty <= 1 ;
@@ -93,7 +88,7 @@
/* Process header */
`HEADER:
begin
- reader_next_state <= `TIMESTAMP;
+ reader_state <= `TIMESTAMP;
if (tx_strobe == 1)
tx_empty <= 1 ;
@@ -114,7 +109,7 @@
`TIMESTAMP:
begin
timestamp <= fifodata;
- reader_next_state <= `WAIT;
+ reader_state <= `WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
@@ -127,16 +122,16 @@
// Wait a little bit more
if (timestamp > adc_time + `JITTER)
- reader_next_state <= `WAIT;
+ reader_state <= `WAIT;
// Let's send it
else if ((timestamp < adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
- reader_next_state <= `WAITSTROBE;
+ reader_state <= `WAITSTROBE;
// Outdated
else if (timestamp < adc_time)
begin
- reader_next_state <= `DISCARD;
+ reader_state <= `DISCARD;
skip <= 1;
end
end
@@ -147,14 +142,14 @@
// If end of payload...
if (read_len == payload_len)
begin
- reader_next_state <= `DISCARD;
+ reader_state <= `DISCARD;
skip <= (payload_len < MAX_PAYLOAD);
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
- reader_next_state <= `SEND;
+ reader_state <= `SEND;
rdreq <= 1;
end
end
@@ -162,8 +157,8 @@
// Send the samples to the tx_chain
`SEND:
begin
- reader_next_state <= `WAITSTROBE;
- read_len <= read_len + 4;
+ reader_state <= `WAITSTROBE;
+ read_len <= read_len + 9'd4;
tx_empty <= 0;
rdreq <= 0;
@@ -186,7 +181,7 @@
`DISCARD:
begin
skip <= 0;
- reader_next_state <= `IDLE;
+ reader_state <= `IDLE;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
@@ -195,7 +190,6 @@
begin
$display ("Error unknown state");
reader_state <= `IDLE;
- reader_next_state <= `IDLE;
end
endcase
end
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -32,24 +32,20 @@
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
- always @(usb_ram_ain, usb_ram_aout, reset)
+ always @(usb_ram_ain, usb_ram_aout, isfull)
begin
- if (reset)
- pkt_waiting <= 0;
- else if (usb_ram_ain == usb_ram_aout)
+ if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull ;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= usb_ram_ain - usb_ram_aout >= PKT_DEPTH;
else
pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >=
PKT_DEPTH;
end
-
+
// Check if there is room
- always @(usb_ram_ain, usb_ram_aout, reset)
+ always @(usb_ram_ain, usb_ram_aout, isfull)
begin
- if (reset)
- have_space <= 1;
- else if (usb_ram_ain == usb_ram_aout)
+ if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH *
(NUM_PACKETS - 1))? 1'b1 : 1'b0;
@@ -57,6 +53,8 @@
have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
+
+
/* RAM Writing/Reading process */
always @(posedge clock)
begin
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -7,8 +7,8 @@
parameter NUM_CHAN = 2 ;
/* Debug paramters */
- parameter STROBE_RATE_0 = 1 ;
- parameter STROBE_RATE_1 = 2 ;
+ parameter STROBE_RATE_0 = 8'd1 ;
+ parameter STROBE_RATE_1 = 8'd2 ;
input wire usbclk ;
input wire bus_reset ; // Used here for the 257-Hack to
fix the FX2 bug
@@ -29,7 +29,7 @@
output wire [15:0] tx_i_1 ;
output wire [15:0] tx_q_1 ;
/* Not used yet */
- output wire [11:0] debugbus ;
+ output wire [15:0] debugbus ;
output wire [15:0] tx_i_2 ;
output wire [15:0] tx_q_2 ;
output wire [15:0] tx_i_3 ;
@@ -40,7 +40,7 @@
/* These will eventually be external register */
reg [31:0] time_counter ;
- wire [7:0] txstrobe_rate [NUM_CHAN:0] ;
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
@@ -70,7 +70,7 @@
wire tdpf_rdreq [NUM_CHAN:0] ;
wire tdpf_skip [NUM_CHAN:0] ;
wire [NUM_CHAN:0] tdpf_have_space ;
- wire txstrobe_chan [NUM_CHAN:0] ;
+ wire txstrobe_chan [NUM_CHAN-1:0] ;
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
@@ -90,15 +90,22 @@
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
- assign tx_q_2 = 16'b0 ;
- assign tx_i_2 = 16'b0 ;
- assign tx_q_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
- assign debugbus = 12'b0 ;
+ assign tx_q_2 = 16'b0 ;
+ assign tx_i_2 = 16'b0 ;
+ assign tx_q_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ /*assign debugbus = {7'b0, have_space, tx_empty, WR,
tdpf_have_space[0],
+ tdpf_have_space[1], bus_reset, reset, txempty_chan[0],
+ txempty_chan[1]} ;*/
+
+ assign debugbus = {3'b0, txclk, have_space, tupf_pkt_waiting,
tdpf_pkt_waiting[0],
+ tdpf_pkt_waiting[1], tx_empty, WR, tdpf_have_space[0],
+ tdpf_have_space[1], bus_reset, reset, txempty_chan[0],
+ txempty_chan[1]} ;
usb_fifo_writer tx_usb_packet_writer
- ( .reset (reset),
+ ( .reset (bus_reset),
.usb_clock (usbclk),
.write_enable_fx2 (WR),
.bus_data (usbdata),
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -32,7 +32,6 @@
/* Local registers */
reg [2:0] reader_state ;
- reg [2:0] reader_next_state ;
reg [4:0] channel ;
reg [9:0] pkt_length ;
reg [9:0] read_length ;
@@ -42,20 +41,18 @@
begin
if (reset)
begin
- reader_state <= `IDLE ;
- reader_next_state <= `IDLE ;
+ reader_state <= `IDLE ;
rdreq <= 0 ;
WR_chan <= {NUM_CHAN+1{1'b0}} ;
done_chan <= {NUM_CHAN+1{1'b0}} ;
end
else
begin
- reader_state = reader_next_state ;
case(reader_state)
`IDLE:
begin
- reader_next_state <= pkt_waiting ? `WAIT :
`IDLE ;
+ reader_state <= pkt_waiting ? `WAIT : `IDLE
;
done_chan <= {NUM_CHAN+1{1'b0}} ;
rdreq <= pkt_waiting ;
end
@@ -63,7 +60,7 @@
/* Wait for the fifo's data to show up */
`WAIT:
begin
- reader_next_state <= `READ_HEADER ;
+ reader_state <= `READ_HEADER ;
rdreq <= 0 ;
end
@@ -71,24 +68,24 @@
begin
/* Read header fields */
channel <= (fifodata[20:16]) ;
- pkt_length <= fifodata[8:0] + 8 ;
+ pkt_length <= fifodata[8:0] + 10'd8 ;
read_length <= 10'd0 ;
if (have_space_chan[channel])
begin
- reader_next_state <= `FORWARD_DATA ;
+ reader_state <= `FORWARD_DATA ;
rdreq <= 1;
end
end
`FORWARD_DATA:
begin
- read_length <= read_length + 4 ;
+ read_length <= read_length + 10'd4 ;
// If end of payload...
if (read_length == pkt_length)
begin
- reader_next_state <= rdreq ? `SKIP_REST : `IDLE ;
+ reader_state <= rdreq ? `SKIP_REST : `IDLE ;
/* Data pushing done */
WR_chan <= {NUM_CHAN+1{1'b0}} ;
@@ -109,11 +106,11 @@
`SKIP_REST:
begin
- read_length <= read_length + 4;
+ read_length <= read_length + 10'd4;
done_chan <= {NUM_CHAN+1{1'b0}} ;
if (read_length == PKT_SIZE - 4)
- reader_next_state <= `IDLE ;
+ reader_state <= `IDLE ;
else if (read_length == PKT_SIZE - 8)
rdreq <= 0 ;
end
@@ -121,7 +118,6 @@
default:
begin
reader_state <= `IDLE;
- reader_next_state <= `IDLE;
end
endcase
end
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/master_control.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/master_control.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/master_control.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -22,6 +22,10 @@
// Clock, enable, and reset controls for whole system
+`include "config.vh"
+`include "../../firmware/include/fpga_regs_common.v"
+`include "../../firmware/include/fpga_regs_standard.v"
+
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire
serial_strobe,
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/rx_buffer.v
2007-06-04 18:49:57 UTC (rev 5666)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/rx_buffer.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -77,6 +77,7 @@
else
read_count <= #1 RD ? read_count : 9'b0;
+ reg [3:0] store_next;
// Detect overrun
always @(posedge rxclk)
if(reset)
@@ -86,7 +87,6 @@
else if(clear_status)
rx_overrun <= 1'b0;
- reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
@@ -100,9 +100,9 @@
store_next <= #1 store_next + 4'd1;
assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
-
+
+ reg [15:0] top,bottom;
assign fifodata_8 = {round_8(top),round_8(bottom)};
- reg [15:0] top,bottom;
function [7:0] round_8;
input [15:0] in_val;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-04 19:24:30 UTC (rev 5667)
@@ -1,4 +1,4 @@
-// -*- verilog -*-
+ // -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
@@ -31,10 +31,10 @@
// ====================================================================
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
-//`include "../include/common_config_1rxhb_1tx.vh"
+ `include "../include/common_config_1rxhb_1tx.vh"
// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
- `include "../include/common_config_2rxhb_2tx.vh"
+//`include "../include/common_config_2rxhb_2tx.vh"
// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
//`include "../include/common_config_4rx_0tx.vh"
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-04 18:49:57 UTC (rev 5666)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -19,7 +19,7 @@
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`define IN_BAND
+//`define IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
@@ -326,7 +326,7 @@
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_0(tx_debugbus),.debug_1(tx_debugbus),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-04 18:49:57 UTC (rev 5666)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-04 19:24:30 UTC (rev 5667)
@@ -6,6 +6,7 @@
reg usbclock;
reg txclock;
reg reset;
+reg bus_reset;
reg [7:0] i;
reg [15:0] usbdata;
reg WR;
@@ -25,7 +26,6 @@
wire ok;
/* NOT USED YET */
-reg bus_reset;
reg clear_status;
reg channels;
@@ -47,7 +47,7 @@
.tx_q_1(tx_q_1),
.tx_q_2(tx_q_2),
.tx_q_3(tx_q_3),
- .bus_reset(1'b0),
+ .bus_reset(bus_reset),
.clear_status(1'b0),
.channels(4'b0),
.debugbus()
@@ -80,6 +80,7 @@
txclock = 0;
WR = 0;
reset = 1;
+ bus_reset = 1;
i = 0;
bus_reset = 0;
@@ -87,6 +88,7 @@
channels = 0;
#40 reset = 0;
+ bus_reset = 0;
if (file == 0)
begin
@@ -109,33 +111,36 @@
$display("Done reading packets.dat");
$finish;
end
-
- // Wait
- i = 0;
- while(have_space == 0)
- begin
- @(posedge usbclock)
+ else if (r == 512)
+ begin
+ // Wait
i = 0;
- end
+ while(have_space == 0)
+ begin
+ @(posedge usbclock)
+ i = 0;
+ end
- repeat (256) begin
- @(posedge usbclock)
- WR = 1;
- usbdata = {packet[2*i+1],packet[2*i]};
- i = i + 1 ;
+ repeat (256) begin
+ @(posedge usbclock)
+ WR = 1;
+ usbdata = {packet[2*i+1],packet[2*i]};
+ i = i + 1 ;
+ end
+ @(posedge usbclock)
+ WR = 0;
+ /*@(posedge usbclock)
+ WR = 0;*/
end
- @(posedge usbclock)
- WR = 0;
- @(posedge usbclock)
- WR = 0;
end
-
+
+ $display("Closing file...");
$fclose(file);
end
always
- #2 usbclock = ~ usbclock;
+ #5 usbclock = ~ usbclock;
always
- #5 txclock = ~ txclock;
+ #2 txclock = ~ txclock;
endmodule
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-04
18:49:57 UTC (rev 5666)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-04
19:24:30 UTC (rev 5667)
@@ -243,43 +243,159 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 18
-Project_File_0 = ./strobe_gen_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = ./usb_fifo_writer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = Z:/wc/simulations/data_packet_fifo_test.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Files_Count = 76
+Project_File_0 = Z:/wc/inband/usrp/fpga/sdr_lib/setting_reg.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726985 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
69 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = Z:/wc/inband/usrp/fpga/sdr_lib/master_control.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
56 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = Z:/wc/inband/usrp/fpga/sdr_lib/ext_fifo.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
53 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
17 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = ./fake_fx2_test.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = ./fake_fx2.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180848225 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180839053 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180839253 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180847316 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180832728 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_10 = ./chan_fifo_readers_test.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ./usb_packet_fifo_test.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = ./tx_buffer_test.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_17 = ./usb_fifo_reader_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = Z:/wc/inband/usrp/fpga/megacells/clk_doubler.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727112 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = Z:/wc/inband/usrp/fpga/models/bustri.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726992 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/ram16.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726978 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
60 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = Z:/wc/inband/usrp/fpga/megacells/dspclkpll.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = Z:/wc/inband/usrp/fpga/sdr_lib/bidir_reg.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
42 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = Z:/wc/inband/usrp/fpga/models/fifo.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726992 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 31
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = Z:/wc/inband/usrp/fpga/sdr_lib/ddc.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
50 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ./chan_fifo_readers_test.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180832728 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = Z:/wc/inband/usrp/fpga/megacells/accum32.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = Z:/wc/inband/usrp/fpga/megacells/add32.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = Z:/wc/inband/usrp/fpga/models/fifo_1k.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 35
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_16 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
72 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = ./usb_packet_fifo_test.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_18 = Z:/wc/inband/usrp/fpga/sdr_lib/master_control_multi.v
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
57 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_19 = Z:/wc/inband/usrp/fpga/sdr_lib/gen_sync.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
54 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_20 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180923485 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_21 = ./tx_buffer_test.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = Z:/wc/inband/usrp/fpga/models/fifo_1c_1k.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 32
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_24 = Z:/wc/inband/usrp/fpga/sdr_lib/clk_divider.v
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
47 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_25 = Z:/wc/inband/usrp/fpga/sdr_lib/cic_interp.v
+Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
46 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_26 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_27 = Z:/wc/inband/usrp/fpga/sdr_lib/rx_chain.v
+Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
65 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_28 =
Z:/wc/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
+Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 75
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_29 = Z:/wc/inband/usrp/fpga/models/fifo_4k.v
+Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 37
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_30 = Z:/wc/inband/usrp/fpga/megacells/fifo_4k.v
+Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
27 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_31 = Z:/wc/inband/usrp/fpga/sdr_lib/rx_chain_dual.v
+Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_32 = Z:/wc/inband/usrp/fpga/sdr_lib/io_pins.v
+Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
55 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_33 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922343 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_34 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922563 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_35 = Z:/wc/inband/usrp/fpga/models/fifo_1c_4k.v
+Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 34
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_36 = Z:/wc/inband/usrp/fpga/sdr_lib/cordic.v
+Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_37 = Z:/wc/inband/usrp/fpga/sdr_lib/cic_int_shifter.v
+Project_File_P_37 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
45 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_38 = Z:/wc/inband/usrp/fpga/megacells/pll.v
+Project_File_P_38 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
29 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_39 = Z:/wc/inband/usrp/fpga/sdr_lib/serial_io.v
+Project_File_P_39 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
68 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_40 = Z:/wc/inband/usrp/fpga/sdr_lib/ram64.v
+Project_File_P_40 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
62 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_41 = Z:/wc/inband/usrp/fpga/models/fifo_2k.v
+Project_File_P_41 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 36
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_42 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
+Project_File_P_42 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
73 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_43 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
+Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
26 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_44 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain_hb.v
+Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
74 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_45 = Z:/wc/inband/usrp/fpga/sdr_lib/rx_dcoffset.v
+Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
67 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_46 = ./fake_fx2_test.v
+Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_47 = Z:/wc/inband/usrp/fpga/sdr_lib/sign_extend.v
+Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726985 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_48 = Z:/wc/inband/usrp/fpga/models/fifo_1c_2k.v
+Project_File_P_48 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726991 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 33
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_49 = Z:/wc/inband/usrp/fpga/sdr_lib/rx_buffer.v
+Project_File_P_49 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_50 = Z:/wc/inband/usrp/fpga/models/ssram.v
+Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 39
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_51 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_52 = Z:/wc/inband/usrp/fpga/sdr_lib/cordic_stage.v
+Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_53 = ./usb_fifo_reader_test.v
+Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_54 = Z:/wc/inband/usrp/fpga/megacells/addsub16.v
+Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_55 = Z:/wc/inband/usrp/fpga/sdr_lib/adc_interface.v
+Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_56 = Z:/wc/inband/usrp/fpga/sdr_lib/rssi.v
+Project_File_P_56 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
63 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_57 = ./strobe_gen_test.v
+Project_File_P_57 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_58 = ./usb_fifo_writer_test.v
+Project_File_P_58 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_59 = Z:/wc/inband/usrp/fpga/sdr_lib/duc.v
+Project_File_P_59 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_60 = Z:/wc/inband/usrp/fpga/sdr_lib/ram32.v
+Project_File_P_60 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726978 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_61 = Z:/wc/inband/usrp/fpga/megacells/sub32.v
+Project_File_P_61 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727111 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
25 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_62 = Z:/wc/inband/usrp/fpga/sdr_lib/cic_dec_shifter.v
+Project_File_P_62 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726983 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_63 = Z:/wc/inband/usrp/fpga/sdr_lib/ram.v
+Project_File_P_63 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_64 = ./fake_fx2.v
+Project_File_P_64 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180969005 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_65 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_65 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180922278 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_66 = Z:/wc/inband/usrp/fpga/sdr_lib/dpram.v
+Project_File_P_66 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_67 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_67 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_68 = Z:/wc/inband/usrp/fpga/models/pll.v
+Project_File_P_68 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 38
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_69 = Z:/wc/inband/usrp/fpga/sdr_lib/atr_delay.v
+Project_File_P_69 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_70 = Z:/wc/simulations/full_chip.v
+Project_File_P_70 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180972912 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_71 = Z:/wc/inband/usrp/fpga/sdr_lib/setting_reg_masked.v
+Project_File_P_71 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_72 = Z:/wc/inband/usrp/fpga/sdr_lib/phase_acc.v
+Project_File_P_72 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726980 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
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+Project_File_73 = Z:/wc/inband/usrp/fpga/megacells/bustri.v
+Project_File_P_73 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727112 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_74 = Z:/wc/inband/usrp/fpga/megacells/mylpm_addsub.v
+Project_File_P_74 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
28 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_75 = Z:/wc/inband/usrp/fpga/sdr_lib/cic_decim.v
+Project_File_P_75 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726984 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
44 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -309,6 +425,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 0}
{Z:/wc/simulations/fake_tx_chain.v 0 0}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/fake_fx2_test.v 0 0}
{Z:/wc/simulations/fake_tx_chain.v 0 0} {Z:/wc/simulations/full_chip.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
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- [Commit-gnuradio] r5667 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/sdr_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations,
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