[Commit-gnuradio] r5796 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-19 02:57:48 -0600 (Tue, 19 Jun 2007)
New Revision: 5796

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
should compile, but icarus chokes for some reason


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-19 07:24:18 UTC (rev 5795)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-19 08:57:48 UTC (rev 5796)
@@ -25,6 +25,8 @@
    
    input stream_clk,
    input stream_rst,
+
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
    
    // Write Interfaces
    input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, output 
wr0_ready_o, output wr0_full_o,
@@ -37,101 +39,78 @@
 
    assign wb_err_o = 1'b0;  // Unused for now
    assign wb_rty_o = 1'b0;  // Unused for now
-   
+
    wire [7:0] sel_a;
-   wire [31:0] buf0_outa, buf1_outa, buf2_outa, buf3_outa, buf4_outa, 
buf5_outa, buf6_outa, buf7_outa;
 
    wire [2:0]  which_buf = wb_adr_i[13:11];   // address 15:14 selects the 
buffer pool
-   wire [8:0]  buf_addr = wb_adr_i[10:2];     // ignore address 1:0, 32-bit 
access only
+   wire [8:0]  buf_addra = wb_adr_i[10:2];     // ignore address 1:0, 32-bit 
access only
  
-   wire        buf0_dir, buf1_dir, buf2_dir, buf3_dir,
-              buf4_dir, buf5_dir, buf6_dir, buf7_dir;
-   wire [1:0]  buf0_sel, buf1_sel, buf2_sel, buf3_sel,
-              buf4_sel, buf5_sel, buf6_sel, buf7_sel;
-   wire [8:0]  buf0_start, buf1_start, buf2_start, buf3_start, 
-              buf4_start, buf5_start, buf6_start, buf7_start;
-   wire [8:0]  buf0_end, buf1_end, buf2_end, buf3_end, 
-              buf4_end, buf5_end, buf6_end, buf7_end;
-   
    decoder_3_8 dec(.sel(which_buf),.res(sel_a));
 
-   wire [31:0] b0di, b0do, b1di, b1do, b2di, b2do, b3di, b3do,
-              b4di, b4do, b5di, b5do, b6di, b6do, b7di, b7do;
+   genvar      i;
 
-   wire        b0enb, b1enb, b2enb, b3enb, b4enb, b5enb, b6enb, b7enb;
-   wire        b0web, b1web, b2web, b3web, b4web, b5web, b6web, b7web;   
+   wire [8:0]  fl[0:7];
+   wire [8:0]  ll[0:7];
+   wire [3:0]  step[0:7];
+   wire        read_go[0:7];
+   wire        write_go[0:7];
+   wire [1:0]  read_port[0:7];
+   wire [1:0]  write_port[0:7];
+   wire [3:0]  dummy[0:7];
+   wire        changed [0:7];
 
-   wire [8:0]  b0a, b1a, b2a, b3a, b4a, b5a, b6a, b7a;
+   wire [31:0] buf_doa[0:7];
    
-   buffer_2k buf_0
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[0]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf0_outa),
-      
.clkb(stream_clk),.enb(b0enb),.web(b0web),.addrb(b0a),.dib(b0di),.dob(b0do));
+   wire        buf_enb[0:7];
+   wire        buf_web[0:7];
+   wire [8:0]  buf_addrb[0:7];
+   wire [31:0] buf_dib[0:7];
+   wire [31:0] buf_dob[0:7];
    
-   fifo_int fifo_int_0
-     
(.clk(stream_clk),.rst(stream_rst),.firstline(),.lastline(),.step(),.read_go(),.write_go(),.done(),
-      
.en_o(b0enb),.we_o(b0web),.addr_o(b0a),.dat_to_buf(b0di),.dat_from_buf(b0do),
-      
.wr_dat_i(wr0_dat_i),.wr_write_i(wr0_write_i),.wr_done_i(wr0_done_i),.wr_ready_o(wr0_ready_o),.wr_full_o(wr0_full_o),
-      
.rd_dat_o(rd0_dat_o),.rd_read_i(rd0_read_i),.rd_done_i(rd0_done_i),.rd_ready_o(rd0_ready_o),.rd_empty_o(rd0_empty_o)
-      );
-   
-   buffer_2k buf_1
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[1]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf1_outa),
-      
.clkb(stream_clk),.enb(b1enb),.web(b1web),.addrb(b1a),.dib(b1di),.dob(b1do));
-   
-   fifo_int fifo_int_1
-     
(.clk(stream_clk),.rst(stream_rst),.firstline(),.lastline(),.step(),.read_go(),.write_go(),.done(),
-      
.en_o(b1enb),.we_o(b1web),.addr_o(b1a),.dat_to_buf(b1di),.dat_from_buf(b1do),
-      
.wr_dat_i(wr1_dat_i),.wr_write_i(wr1_write_i),.wr_done_i(wr1_done_i),.wr_ready_o(wr1_ready_o),.wr_full_o(wr1_full_o),
-      
.rd_dat_o(rd1_dat_o),.rd_read_i(rd1_read_i),.rd_done_i(rd1_done_i),.rd_ready_o(rd1_ready_o),.rd_empty_o(rd1_empty_o)
-      );
+   wire        done[0:7];
 
-   /*
-   buffer_2k buf_2
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[2]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf2_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b2a),.dib(b2di),.dob(b2do));
+   wire [31:0] wr_dat_i[0:7];
+   wire        wr_write_i[0:7];
+   wire        wr_done_i[0:7];
+   wire        wr_ready_o[0:7];
+   wire        wr_full_o[0:7];
+
+   wire [31:0] rd_dat_o[0:7];
+   wire        rd_read_i[0:7];
+   wire        rd_done_i[0:7];
+   wire        rd_ready_o[0:7];
+   wire        rd_empty_o[0:7];
    
-   buffer_2k buf_3
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[3]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf3_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b3a),.dib(b3di),.dob(b3do));
    
-   buffer_2k buf_4
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[4]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf4_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b4a),.dib(b4di),.dob(b4do));
+   generate
+      for(i=0;i<8;i=i+1)
+       begin : gen_buffer
+          setting_reg #(.my_addr(i)) 
+            
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
+                 
.out({dummy[i],read_port[i],write_port[i],write_go[i],read_go[i],step[i],ll[i],fl[i]}),.changed(changed[i]));
+          buffer_2k buffer_2k
+            (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
+             .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
+             
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
 
+          fifo_int fifo_int
+            
(.clk(stream_clk),.rst(stream_rst),.firstline(fl[i]),.lastline(ll[i]),
+             
.step(step[i]),.read_go(changed[i]&read_go[i]),.write_go(changed[i]&write_go[i]),.done(done[i]),
+             
.en_o(buf_enb[i]),.we_o(buf_web[i]),.addr_o(buf_addrb[i]),.dat_to_buf(buf_dib[i]),.dat_from_buf(buf_dob[i]),
+             
.wr_dat_i(wr_dat_i[i]),.wr_write_i(wr_write_i[i]),.wr_done_i(wr_done_i[i]),
+             .wr_ready_o(wr_ready_o[i]),.wr_full_o(wr_full_o[i]),
+             
.rd_dat_o(rd_dat_o[i]),.rd_read_i(rd_read_i[i]),.rd_done_i(rd_done_i[i]),
+             .rd_ready_o(rd_ready_o[i]),.rd_empty_o(rd_empty_o[i]) 
+             );
+       end
+   endgenerate
    
-   buffer_2k buf_5
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[5]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf5_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b5a),.dib(b5di),.dob(b5do));
-   
-   buffer_2k buf_6
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[6]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf6_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b6a),.dib(b6di),.dob(b6do));
-   
-   buffer_2k buf_7
-     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[7]),.wea(wb_we_i),
-      .addra(buf_addr),.dia(wb_dat_i),.doa(buf7_outa),
-      .clkb(stream_clk),.enb(1),.web(),.addrb(b7a),.dib(b7di),.dob(b7do));
-   */
-  always @(posedge wb_clk_i)
+   always @(posedge wb_clk_i)
      if(wb_stb_i)
-       case(which_buf)
-        3'd0 : wb_dat_o <= buf0_outa;
-        3'd1 : wb_dat_o <= buf1_outa;
-        3'd2 : wb_dat_o <= buf2_outa;
-        3'd3 : wb_dat_o <= buf3_outa;
-        3'd4 : wb_dat_o <= buf4_outa;
-        3'd5 : wb_dat_o <= buf5_outa;
-        3'd6 : wb_dat_o <= buf6_outa;
-        3'd7 : wb_dat_o <= buf7_outa;
-       endcase // case(which_buf)
+       wb_dat_o <= buf_doa[which_buf];
    
+   
    always @(posedge wb_clk_i)
      wb_ack_o <= wb_stb_i;
    
 endmodule // buffer_pool
+