[Commit-gnuradio] r6577 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-10-02 22:33:38 -0600 (Tue, 02 Oct 2007)
New Revision: 6577

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
Log:
progress


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-02 23:12:57 UTC (rev 6576)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-03 04:33:38 UTC (rev 6577)
@@ -313,3 +313,13 @@
 TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
 TIMESPEC "TS_aux_to_dsp" = FROM "RAM_CE1n" TO "dsp_clk"  TIG;
 TIMESPEC "TS_dsp_to_aux" = FROM "dsp_clk" TO "RAM_CE1n"  TIG;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
+TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
+TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-10-02 23:12:57 UTC (rev 6576)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-10-03 04:33:38 UTC (rev 6577)
@@ -25,10 +25,8 @@
 verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/ram_2port.v"
 verilog work "../../sdr_lib/cordic.v"
 verilog work "../../sdr_lib/cic_interp.v"
@@ -38,6 +36,7 @@
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core.v"
 verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/elastic_buffer.v"
 verilog work "../../eth/rtl/verilog/RMON.v"
 verilog work "../../eth/rtl/verilog/Phy_int.v"
 verilog work "../../eth/rtl/verilog/MAC_tx.v"
@@ -50,13 +49,15 @@
 verilog work "../../control_lib/mux8.v"
 verilog work "../../control_lib/mux4.v"
 verilog work "../../control_lib/longfifo.v"
-verilog work "../../control_lib/fifo_int.v"
 verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/buffer_int.v"
 verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../sdr_lib/tx_control.v"
+verilog work "../../sdr_lib/rx_control.v"
 verilog work "../../sdr_lib/dsp_core_tx.v"
 verilog work "../../sdr_lib/dsp_core_rx.v"
 verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
-verilog work "../../opencores/simple_gpio/rtl/simple_gpio.v"
+verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
 verilog work "../../eth/rtl/verilog/MAC_top.v"
@@ -64,12 +65,14 @@
 verilog work "../../eth/mac_rxfifo_int.v"
 verilog work "../../control_lib/wb_readback_mux.v"
 verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/timer.v"
 verilog work "../../control_lib/system_control.v"
 verilog work "../../control_lib/settings_bus.v"
 verilog work "../../control_lib/serdes_tx.v"
 verilog work "../../control_lib/serdes_rx.v"
 verilog work "../../control_lib/ram_wb_harvard.v"
 verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/nsgpio.v"
 verilog work "../../control_lib/buffer_pool.v"
 verilog work "../u2_basic/u2_basic.v"
 verilog work "u2_fpga_top.v"