[Commit-gnuradio] r6584 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-10-03 16:09:26 -0600 (Wed, 03 Oct 2007)
New Revision: 6584

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
fix timing problems by moving aux_clk clock mux to before DCM instead of after


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-03 22:07:51 UTC (rev 6583)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-03 22:09:26 UTC (rev 6584)
@@ -304,15 +304,15 @@
 #PACE: End of Constraints generated by PACE
 NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
 TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
-NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
-TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
+#NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
+#TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
 #NET "wb_clk" TNM_NET = "wb_clk"
 #TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 2
 NET "cpld_clk" TNM_NET = "cpld_clk";
 NET "dsp_clk" TNM_NET = "dsp_clk";
 TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-TIMESPEC "TS_aux_to_dsp" = FROM "RAM_CE1n" TO "dsp_clk"  TIG;
-TIMESPEC "TS_dsp_to_aux" = FROM "dsp_clk" TO "RAM_CE1n"  TIG;
+#TIMESPEC "TS_aux_to_dsp" = FROM "RAM_CE1n" TO "dsp_clk"  TIG;
+#TIMESPEC "TS_dsp_to_aux" = FROM "dsp_clk" TO "RAM_CE1n"  TIG;
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
 NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-10-03 22:07:51 UTC (rev 6583)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-10-03 22:09:26 UTC (rev 6584)
@@ -165,8 +165,11 @@
    OBUFDS exp_pps_out_pin 
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
    defparam    exp_pps_out_pin.IOSTANDARD = "LVDS_25";
 
-   wire        dcm_rst = ~clock_ready;
+   //wire      dcm_rst = ~clock_ready;
+   wire        dcm_rst = 1'b0;
 
+   wire        clk_muxed = clock_ready ? clk_fpga : aux_clk;
+   
    // Handle Clocks
    DCM DCM_INST (.CLKFB(dsp_clk), 
                  .CLKIN(clk_fpga), 
@@ -202,15 +205,15 @@
    defparam DCM_INST.PHASE_SHIFT = 0;
    defparam DCM_INST.STARTUP_WAIT = "FALSE";
 
-   BUFGMUX wbclk_BUFGMUX (.I0(aux_clk), 
-                          .I1(clk_div), 
-                          .S(clock_ready), 
-                          //.S(1'b0), 
-                          .O(wb_clk));
+   //BUFGMUX wbclk_BUFGMUX (.I0(aux_clk), 
+   //                       .I1(clk_div), 
+   //                       .S(clock_ready), 
+   //                       //.S(1'b0), 
+   //                       .O(wb_clk));
 
-   BUFG dspclk_BUFG (.I(dcm_out), 
-                     .O(dsp_clk));
    
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
 
    // I2C -- Don't use external transistors for open drain, the FPGA 
implements this
    IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));