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[Commit-gnuradio] r6638 - in gnuradio/branches/developers/zhuochen/inban
|
From: |
zhuochen |
|
Subject: |
[Commit-gnuradio] r6638 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_inband_usb |
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Date: |
Tue, 16 Oct 2007 16:36:47 -0600 (MDT) |
Author: zhuochen
Date: 2007-10-16 16:36:47 -0600 (Tue, 16 Oct 2007)
New Revision: 6638
Added:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Adding in register code along with RBFs within install directories to
match the code
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-10-16 21:56:37 UTC (rev 6637)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-10-16 22:36:47 UTC (rev 6638)
@@ -1,12 +1,102 @@
module register_io
- (input clk, input reset, input wire [1:0] enable, input wire [6:0]
addr,
- input wire [31:0] datain, output reg [31:0] dataout, output wire
[15:0] debugbus,
- output reg [6:0] addr_wr, output reg [31:0] data_wr, output wire
strobe_wr,
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- output wire [31:0] threshhold, output wire [31:0] rssi_wait,
- input wire [31:0] readback_0, input wire [31:0] readback_1);
-
+ (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr,
strobe_wr,
+ rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1,
reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate,
decim_rate,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
+
+ input clk;
+ input reset;
+ input wire [1:0] enable;
+ input wire [6:0] addr;
+ input wire [31:0] datain;
+ output reg [31:0] dataout;
+ output wire [15:0] debugbus;
+ output reg [6:0] addr_wr;
+ output reg [31:0] data_wr;
+ output wire strobe_wr;
+ input wire [31:0] rssi_0;
+ input wire [31:0] rssi_1;
+ input wire [31:0] rssi_2;
+ input wire [31:0] rssi_3;
+ output wire [31:0] threshhold;
+ output wire [31:0] rssi_wait;
+ input wire [15:0] reg_0;
+ input wire [15:0] reg_1;
+ input wire [15:0] reg_2;
+ input wire [15:0] reg_3;
+ input wire [11:0] atr_tx_delay;
+ input wire [11:0] atr_rx_delay;
+ input wire [7:0] master_controls;
+ input wire [3:0] debug_en;
+ input wire [15:0] atr_mask_0;
+ input wire [15:0] atr_txval_0;
+ input wire [15:0] atr_rxval_0;
+ input wire [15:0] atr_mask_1;
+ input wire [15:0] atr_txval_1;
+ input wire [15:0] atr_rxval_1;
+ input wire [15:0] atr_mask_2;
+ input wire [15:0] atr_txval_2;
+ input wire [15:0] atr_rxval_2;
+ input wire [15:0] atr_mask_3;
+ input wire [15:0] atr_txval_3;
+ input wire [15:0] atr_rxval_3;
+ input wire [7:0] txa_refclk;
+ input wire [7:0] txb_refclk;
+ input wire [7:0] rxa_refclk;
+ input wire [7:0] rxb_refclk;
+ input wire [7:0] interp_rate;
+ input wire [7:0] decim_rate;
+ input wire [7:0] misc;
+ input wire [31:0] txmux;
+
+ wire [31:0] bundle[43:0];
+ assign bundle[0] = 32'hFFFFFFFF;
+ assign bundle[1] = 32'hFFFFFFFF;
+ assign bundle[2] = {20'd0, atr_tx_delay};
+ assign bundle[3] = {20'd0, atr_rx_delay};
+ assign bundle[4] = {24'sd0, master_controls};
+ assign bundle[5] = 32'hFFFFFFFF;
+ assign bundle[6] = 32'hFFFFFFFF;
+ assign bundle[7] = 32'hFFFFFFFF;
+ assign bundle[8] = 32'hFFFFFFFF;
+ assign bundle[9] = {15'd0, reg_0};
+ assign bundle[10] = {15'd0, reg_1};
+ assign bundle[11] = {15'd0, reg_2};
+ assign bundle[12] = {15'd0, reg_3};
+ assign bundle[13] = {15'd0, misc};
+ assign bundle[14] = {28'd0, debug_en};
+ assign bundle[15] = 32'hFFFFFFFF;
+ assign bundle[16] = 32'hFFFFFFFF;
+ assign bundle[17] = 32'hFFFFFFFF;
+ assign bundle[18] = 32'hFFFFFFFF;
+ assign bundle[19] = 32'hFFFFFFFF;
+ assign bundle[20] = {16'd0, atr_mask_0};
+ assign bundle[21] = {16'd0, atr_txval_0};
+ assign bundle[22] = {16'd0, atr_rxval_0};
+ assign bundle[23] = {16'd0, atr_mask_1};
+ assign bundle[24] = {16'd0, atr_txval_1};
+ assign bundle[25] = {16'd0, atr_rxval_1};
+ assign bundle[26] = {16'd0, atr_mask_2};
+ assign bundle[27] = {16'd0, atr_txval_2};
+ assign bundle[28] = {16'd0, atr_rxval_2};
+ assign bundle[29] = {16'd0, atr_mask_3};
+ assign bundle[30] = {16'd0, atr_txval_3};
+ assign bundle[31] = {16'd0, atr_rxval_3};
+ assign bundle[32] = {24'd0, interp_rate};
+ assign bundle[33] = {24'd0, decim_rate};
+ assign bundle[34] = 32'hFFFFFFFF;
+ assign bundle[35] = 32'hFFFFFFFF;
+ assign bundle[36] = 32'hFFFFFFFF;
+ assign bundle[37] = 32'hFFFFFFFF;
+ assign bundle[38] = 32'hFFFFFFFF;
+ assign bundle[39] = txmux;
+ assign bundle[40] = {24'd0, txa_refclk};
+ assign bundle[41] = {24'd0, rxa_refclk};
+ assign bundle[42] = {24'd0, txb_refclk};
+ assign bundle[43] = {24'd0, rxb_refclk};
+
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
@@ -25,36 +115,12 @@
if (enable[0])
begin
//read
- case (addr)
- 7'd9:
- begin
- dataout <= rssi_0;
- end
- 7'd10:
- begin
- dataout <= rssi_1;
- end
- 7'd11:
- begin
- dataout <= rssi_2;
- end
- 7'd12:
- begin
- dataout <= rssi_3;
- end
- 7'd32:
- begin
- dataout <= readback_0;
- end
- 7'd33:
- begin
- dataout <= readback_1;
- end
- default:
- begin
- dataout <= out[addr[2:0]];
- end
- endcase
+ if (addr <= 7'd43)
+ dataout <= bundle[addr];
+ else if (addr <= 7'd57 && addr >= 7'd50)
+ dataout <= out[addr-7'd50];
+ else
+ dataout <= 32'hFFFFFFFF;
strobe <= 0;
end
else
@@ -68,20 +134,20 @@
end
//register declarations
- setting_reg #(0) setting_reg0(.clock(clk),.reset(reset),
+ setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
- setting_reg #(1) setting_reg1(.clock(clk),.reset(reset),
+ setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
- setting_reg #(2) setting_reg2(.clock(clk),.reset(reset),
+ setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
- setting_reg #(3) setting_reg3(.clock(clk),.reset(reset),
+ setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
- setting_reg #(4) setting_reg4(.clock(clk),.reset(reset),
+ setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
- setting_reg #(5) setting_reg5(.clock(clk),.reset(reset),
+ setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
- setting_reg #(6) setting_reg6(.clock(clk),.reset(reset),
+ setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
- setting_reg #(7) setting_reg7(.clock(clk),.reset(reset),
+ setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
endmodule
\ No newline at end of file
Added:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
2007-10-16 21:56:37 UTC (rev 6637)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
2007-10-16 22:36:47 UTC (rev 6638)
@@ -23,22 +23,64 @@
// Clock, enable, and reset controls for whole system
module master_control
- ( input master_clk, input usbclk,
- input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire
serial_strobe,
- output tx_bus_reset, output rx_bus_reset,
- output wire tx_dsp_reset, output wire rx_dsp_reset,
- output wire enable_tx, output wire enable_rx,
- output wire [7:0] interp_rate, output wire [7:0] decim_rate,
- output tx_sample_strobe, output strobe_interp,
- output rx_sample_strobe, output strobe_decim,
- input tx_empty,
- input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0]
debug_2,input wire [15:0] debug_3,
- output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0]
reg_2, output wire [15:0] reg_3
- );
-
+ (master_clk, usbclk, serial_addr, serial_data, serial_strobe, tx_bus_reset,
rx_bus_reset,
+ tx_dsp_reset, rx_dsp_reset, enable_tx, enable_rx, interp_rate, decim_rate,
+ tx_sample_strobe, strobe_interp, rx_sample_strobe, strobe_decim,
+ tx_empty, debug_0, debug_1, debug_2, debug_3, reg_0, reg_1, reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk);
+
+ input master_clk;
+ input usbclk;
+ input wire [6:0] serial_addr;
+ input wire [31:0] serial_data;
+ input wire serial_strobe;
+ output tx_bus_reset;
+ output rx_bus_reset;
+ output wire tx_dsp_reset;
+ output wire rx_dsp_reset;
+ output wire enable_tx;
+ output wire enable_rx;
+ output wire [7:0] interp_rate;
+ output wire [7:0] decim_rate;
+ output tx_sample_strobe;
+ output strobe_interp;
+ output rx_sample_strobe;
+ output strobe_decim;
+ input tx_empty;
+ input wire [15:0] debug_0;
+ input wire [15:0] debug_1;
+ input wire [15:0] debug_2;
+ input wire [15:0] debug_3;
+ output wire [15:0] reg_0;
+ output wire [15:0] reg_1;
+ output wire [15:0] reg_2;
+ output wire [15:0] reg_3;
+ output wire [11:0] atr_tx_delay;
+ output wire [11:0] atr_rx_delay;
+ output wire [7:0] master_controls;
+ output wire [3:0] debug_en;
+ output wire [15:0] atr_mask_0;
+ output wire [15:0] atr_txval_0;
+ output wire [15:0] atr_rxval_0;
+ output wire [15:0] atr_mask_1;
+ output wire [15:0] atr_txval_1;
+ output wire [15:0] atr_rxval_1;
+ output wire [15:0] atr_mask_2;
+ output wire [15:0] atr_txval_2;
+ output wire [15:0] atr_rxval_2;
+ output wire [15:0] atr_mask_3;
+ output wire [15:0] atr_txval_3;
+ output wire [15:0] atr_rxval_3;
+ output wire [7:0] txa_refclk;
+ output wire [7:0] txb_refclk;
+ output wire [7:0] rxa_refclk;
+ output wire [7:0] rxb_refclk;
+
// FIXME need a separate reset for all control settings
// Master Controls assignments
- wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL)
sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
@@ -79,9 +121,8 @@
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
- wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
- wire [3:0] debug_en, txcvr_ctrl;
+ wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
@@ -114,8 +155,6 @@
wire transmit_now;
wire atr_ctl;
- wire [11:0] atr_tx_delay, atr_rx_delay;
- wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0)
sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0)
sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-16 21:56:37 UTC (rev 6637)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-16 22:36:47 UTC (rev 6638)
@@ -364,13 +364,42 @@
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (addr_db);
-
+
+ //wires for register connection
+ wire [11:0] atr_tx_delay;
+ wire [11:0] atr_rx_delay;
+ wire [7:0] master_controls;
+ wire [3:0] debug_en;
+ wire [15:0] atr_mask_0;
+ wire [15:0] atr_txval_0;
+ wire [15:0] atr_rxval_0;
+ wire [15:0] atr_mask_1;
+ wire [15:0] atr_txval_1;
+ wire [15:0] atr_rxval_1;
+ wire [15:0] atr_mask_2;
+ wire [15:0] atr_txval_2;
+ wire [15:0] atr_rxval_2;
+ wire [15:0] atr_mask_3;
+ wire [15:0] atr_txval_3;
+ wire [15:0] atr_rxval_3;
+ wire [7:0] txa_refclk;
+ wire [7:0] txb_refclk;
+ wire [7:0] rxa_refclk;
+ wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr),
.strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
- .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
- .readback_0(interp_rate), .readback_1(decim_rate));
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
+ .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
+ .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls),
+ .debug_en(debug_en), .atr_mask_0(atr_mask_0),
.atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
+ .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
+ .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
+ .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
reg [15:0] timestop;
wire stop;
@@ -393,11 +422,14 @@
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
- .tx_empty(tx_empty),
- //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- //.debug_0(tx_debugbus),.debug_1(tx_debugbus),
-
//.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun
== 0),rx_overrun,decim_rate}),
- .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+ .tx_empty(tx_empty),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
+ .master_controls(master_controls), .debug_en(debug_en),
+ .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0),
.atr_rxval_0(atr_rxval_0),
+ .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
+ .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
+ .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
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- [Commit-gnuradio] r6638 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_inband_usb,
zhuochen <=