[Commit-gnuradio] r6654 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: sdr_lib toplevel/usrp_inband_usb

[zhuochen]

Author: zhuochen
Date: 2007-10-18 13:25:52 -0600 (Thu, 18 Oct 2007)
New Revision: 6654

Modified:
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
command block is configured to do register io


Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v 
    2007-10-18 17:16:39 UTC (rev 6653)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/sdr_lib/master_control.v 
    2007-10-18 19:25:52 UTC (rev 6654)
@@ -23,64 +23,30 @@
 // Clock, enable, and reset controls for whole system
 
 module master_control
-  (master_clk, usbclk, serial_addr, serial_data, serial_strobe, tx_bus_reset, 
rx_bus_reset,
-   tx_dsp_reset, rx_dsp_reset, enable_tx, enable_rx, interp_rate, decim_rate, 
-   tx_sample_strobe, strobe_interp, rx_sample_strobe, strobe_decim,
-   tx_empty, debug_0, debug_1, debug_2, debug_3, reg_0, reg_1, reg_2, reg_3, 
-   atr_tx_delay, atr_rx_delay, master_controls, debug_en, 
-   atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
-   atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3,
-   txa_refclk, txb_refclk, rxa_refclk, rxb_refclk);   
-
-       input              master_clk;
-       input              usbclk;
-    input wire [6:0]   serial_addr;
-    input wire [31:0]  serial_data;
-    input wire         serial_strobe;
-    output             tx_bus_reset;
-    output             rx_bus_reset;
-    output wire        tx_dsp_reset;
-    output wire        rx_dsp_reset;
-    output wire        enable_tx;
-    output wire        enable_rx;
-    output wire [7:0]  interp_rate;
-       output wire [7:0]  decim_rate;
-    output             tx_sample_strobe;
-    output             strobe_interp;
-    output             rx_sample_strobe;
-       output             strobe_decim;
-    input                         tx_empty;
-    input wire [15:0]  debug_0;
-       input wire [15:0]  debug_1;
-       input wire [15:0]  debug_2;
-       input wire [15:0]  debug_3;
-    output wire [15:0] reg_0;
-       output wire [15:0] reg_1; 
-       output wire [15:0] reg_2; 
-       output wire [15:0] reg_3;
-       output wire [11:0] atr_tx_delay;
-       output wire [11:0] atr_rx_delay;
-       output wire [7:0]  master_controls;
-       output wire [3:0]  debug_en;
-       output wire [15:0] atr_mask_0;
-       output wire [15:0] atr_txval_0;
-       output wire [15:0] atr_rxval_0;
-       output wire [15:0] atr_mask_1;
-       output wire [15:0] atr_txval_1;
-       output wire [15:0] atr_rxval_1;
-       output wire [15:0] atr_mask_2;
-       output wire [15:0] atr_txval_2;
-       output wire [15:0] atr_rxval_2;
-       output wire [15:0] atr_mask_3;
-       output wire [15:0] atr_txval_3;
-       output wire [15:0] atr_rxval_3;
-       output wire [7:0]  txa_refclk;
-       output wire [7:0]  txb_refclk;
-       output wire [7:0]  rxa_refclk;
-       output wire [7:0]  rxb_refclk;   
-
+  ( input master_clk, input usbclk,
+    input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire 
serial_strobe,
+    output tx_bus_reset, output rx_bus_reset,
+    output wire tx_dsp_reset, output wire rx_dsp_reset,
+    output wire enable_tx, output wire enable_rx,
+    output wire [7:0] interp_rate, output wire [7:0] decim_rate,
+    output tx_sample_strobe, output strobe_interp,
+    output rx_sample_strobe, output strobe_decim,
+    input tx_empty,
+    input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] 
debug_2,input wire [15:0] debug_3,
+    output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] 
reg_2, output wire [15:0] reg_3,
+    //the following output is for register reads only
+    output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output 
wire [7:0] master_controls,
+    output wire [3:0] debug_en, 
+    output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire 
[15:0] atr_rxval_0,
+    output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire 
[15:0] atr_rxval_1,
+    output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire 
[15:0] atr_rxval_2,
+    output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire 
[15:0] atr_rxval_3,
+    output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire 
[7:0] rxa_refclk, output wire [7:0] rxb_refclk
+    );
+   
    // FIXME need a separate reset for all control settings 
    // Master Controls assignments
+   //wire [7:0] master_controls;
    setting_reg #(`FR_MASTER_CTRL) 
sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
    assign     enable_tx = master_controls[0];
    assign     enable_rx = master_controls[1];
@@ -121,7 +87,9 @@
    assign tx_bus_reset = tx_reset_bus_sync2;
    assign rx_bus_reset = rx_reset_bus_sync2;
 
+   //wire [7:0]   txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
    wire        txaclk,txbclk,rxaclk,rxbclk;
+   //wire [3:0] debug_en;
    wire [3:0]  txcvr_ctrl;
 
    wire [31:0] txcvr_rxlines, txcvr_txlines;
@@ -155,6 +123,8 @@
 
    wire        transmit_now;
    wire        atr_ctl;
+   //wire [11:0] atr_tx_delay, atr_rx_delay;
+   //wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, 
atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, 
atr_txval_3, atr_rxval_3;
       
    setting_reg #(`FR_ATR_MASK_0) 
sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
    setting_reg #(`FR_ATR_TXVAL_0) 
sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));

Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
 2007-10-18 17:16:39 UTC (rev 6653)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
 2007-10-18 19:25:52 UTC (rev 6654)
@@ -392,7 +392,6 @@
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v

Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
   2007-10-18 17:16:39 UTC (rev 6653)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
   2007-10-18 19:25:52 UTC (rev 6654)
@@ -363,7 +363,10 @@
    wire strobe_db;
    assign serial_strobe = strobe_db | strobe_wr;
    assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
-   assign serial_data = (strobe_db)? (data_db) : (addr_db);    
+   assign serial_data = (strobe_db)? (data_db) : (data_wr);    
+   //assign serial_strobe = strobe_wr;
+   //assign serial_data = data_wr;
+   //assign serial_addr = addr_wr;
 
    //wires for register connection
        wire [11:0] atr_tx_delay;