[Commit-gnuradio] r6668 - gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband

[gnychis]

Author: gnychis
Date: 2007-10-22 00:38:28 -0600 (Mon, 22 Oct 2007)
New Revision: 6668

Modified:
   
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.cc
   
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.h
Log:
Work in progress on initializing USRP with new register access only


Modified: 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.cc
===================================================================
--- 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.cc 
    2007-10-22 03:52:26 UTC (rev 6667)
+++ 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.cc 
    2007-10-22 06:38:28 UTC (rev 6668)
@@ -28,6 +28,8 @@
 #include <mb_class_registry.h>
 #include <vector>
 #include <usrp_usb_interface.h>
+#include <fpga_regs_common.h>
+#include <fpga_regs_standard.h>
 
 #include <symbols_usrp_server_cs.h>
 #include <symbols_usrp_channel.h>
@@ -51,14 +53,43 @@
 
 usrp_server::usrp_server(mb_runtime *rt, const std::string &instance_name, 
pmt_t user_arg)
   : mb_mblock(rt, instance_name, user_arg),
+  d_fpga_debug(false),
+  d_interp_tx(128),     // these should match the lower level defaults (rx 
also)
+  d_decim_rx(128),
   d_fake_rx(false)
 {
   if(verbose)
     std::cout << "[USRP_SERVER] Initializing...\n";
 
   // Dictionary for arguments to all of the components
-  pmt_t usrp_dict = user_arg;
+  d_usrp_dict = user_arg;
   
+  if (pmt_is_dict(d_usrp_dict)) {
+
+    if(pmt_t fpga_debug = pmt_dict_ref(d_usrp_dict, 
+                                      pmt_intern("fpga-debug"), 
+                                      PMT_NIL)) {
+      if(pmt_eqv(fpga_debug, PMT_T)) 
+        d_fpga_debug=true;
+    }
+    
+    // Read the TX interpolations
+    if(pmt_t interp_tx = pmt_dict_ref(d_usrp_dict, 
+                                      pmt_intern("interp-tx"), 
+                                      PMT_NIL)) {
+      if(!pmt_eqv(interp_tx, PMT_NIL)) 
+        d_interp_tx = pmt_to_long(interp_tx);
+    }
+    
+    // Read the RX decimation rate
+    if(pmt_t decim_rx = pmt_dict_ref(d_usrp_dict, 
+                                      pmt_intern("decim-rx"), 
+                                      PMT_NIL)) {
+      if(!pmt_eqv(decim_rx, PMT_NIL)) 
+        d_decim_rx = pmt_to_long(decim_rx);
+    }
+  }
+  
   // control & status port
   d_cs = define_port("cs", "usrp-server-cs", true, mb_port::EXTERNAL); 
   d_cs_usrp = define_port("cs_usrp", "usrp-interface-cs", false, 
mb_port::INTERNAL);   
@@ -80,7 +111,7 @@
                                mb_port::EXTERNAL));
   }
 
-  define_component("usrp", "usrp_usb_interface", usrp_dict);
+  define_component("usrp", "usrp_usb_interface", d_usrp_dict);
   connect("self", "cs_usrp", "usrp", "cs");
 
   d_defer=false;
@@ -176,6 +207,8 @@
       pmt_t status = pmt_nth(1, data);
       d_cs->send(s_response_open, pmt_list2(invocation_handle, status));
 
+      initialize_registers();
+
       if(pmt_eqv(status,PMT_T)) {
         d_opened = true;
         d_defer = false;
@@ -1387,4 +1420,109 @@
   return -1;
 }
 
+// Need to initialize several registers according to the specified settings of
+// the user
+//
+// FIXME: I believe this is specific to the basic daughterboards, this would
+// need to change when daughterboard support is added
+void
+usrp_server::initialize_registers()
+{
+  // We use handle_cmd_to_control_channel() to create the register writes using
+  // PMT_NIL as the response port to tell usrp_server not to pass the response
+  // up to any application.
+  if(verbose)
+    std::cout << "[USRP_SERVER] Initializing registers...\n";
+
+  // RX mode to normal (0)
+  set_register(FR_MODE, 0);
+
+  // FPGA debugging?
+  if(d_fpga_debug) {
+    set_register(FR_DEBUG_EN, 1);
+    // FIXME: need to figure out exact register writes to control daughterboard
+    // pins that need to be written to
+  } else {
+    set_register(FR_DEBUG_EN, 0);
+  }
+
+  // Set the transmit sample rate divisor, which is 4-1
+  set_register(FR_TX_SAMPLE_RATE_DIV, 3);
+
+  // Dboard IO buffer and register settings
+  set_register(FR_OE_0, (0xffff << 16) | 0x0000);
+  set_register(FR_IO_0, (0xffff << 16) | 0x0000);
+  set_register(FR_OE_1, (0xffff << 16) | 0x0000);
+  set_register(FR_IO_1, (0xffff << 16) | 0x0000);
+  set_register(FR_OE_2, (0xffff << 16) | 0x0000);
+  set_register(FR_IO_2, (0xffff << 16) | 0x0000);
+  set_register(FR_OE_3, (0xffff << 16) | 0x0000);
+  set_register(FR_IO_3, (0xffff << 16) | 0x0000);
+
+  // zero Tx side Auto Transmit/Receive regs
+  set_register(FR_ATR_MASK_0, 0); 
+  set_register(FR_ATR_TXVAL_0, 0);
+  set_register(FR_ATR_RXVAL_0, 0);
+  set_register(FR_ATR_MASK_1, 0); 
+  set_register(FR_ATR_TXVAL_1, 0);
+  set_register(FR_ATR_RXVAL_1, 0);
+  set_register(FR_ATR_MASK_2, 0);
+  set_register(FR_ATR_TXVAL_2, 0);
+  set_register(FR_ATR_RXVAL_2, 0);
+  set_register(FR_ATR_MASK_3, 0);
+  set_register(FR_ATR_TXVAL_3, 0);
+  set_register(FR_ATR_RXVAL_3, 0);
+
+  // Configure TX mux, this is a hacked value
+  set_register(FR_TX_MUX, 0x00000081);
+
+  // Set the interpolation rate, which is the rate divided by 4, minus 1
+  set_register(FR_INTERP_RATE, (d_interp_tx/4)-1);
+
+  // Apparently this register changes again
+  set_register(FR_TX_MUX, 0x00000981);
+
+  // Set the receive sample rate divisor, which is 2-1
+  set_register(FR_RX_SAMPLE_RATE_DIV, 1);
+
+  // DC offset
+  set_register(FR_DC_OFFSET_CL_EN, 0x0000000f);
+
+  // Reset the DC correction offsets
+  set_register(FR_ADC_OFFSET_0, 0);
+  set_register(FR_ADC_OFFSET_1, 0);
+
+  // Some hard-coded RX configuration
+  set_register(FR_RX_FORMAT, 0x00000300);
+  set_register(FR_RX_MUX, 1);
+
+  // RX decimation rate is divided by two, then subtract 1
+  set_register(FR_DECIM_RATE, (d_decim_rx/2)-1);
+
+  // More hard coding
+  set_register(FR_RX_MUX, 0x000e4e41);
+
+  // Resetting RX registers
+  set_register(FR_RX_PHASE_0, 0);
+  set_register(FR_RX_PHASE_1, 0);
+  set_register(FR_RX_PHASE_2, 0);
+  set_register(FR_RX_PHASE_3, 0);
+  set_register(FR_RX_FREQ_0, 0x28000000);
+  set_register(FR_RX_FREQ_1, 0);
+  set_register(FR_RX_FREQ_2, 0);
+  set_register(FR_RX_FREQ_3, 0);
+
+}
+
+// THIS IS ONLY FOR INTERNAL USRP_SERVER USAGE
+void
+usrp_server::set_register(long reg, long val)
+{
+  handle_cmd_to_control_channel(d_tx[0], d_chaninfo_tx,
+    pmt_list2(PMT_NIL,  // empty invoc handle
+              pmt_list1(pmt_list2(s_op_write_reg,
+                        pmt_list2(pmt_from_long(reg),
+                                  pmt_from_long(val))))));
+}
+
 REGISTER_MBLOCK_CLASS(usrp_server);

Modified: 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.h
===================================================================
--- 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.h  
    2007-10-22 03:52:26 UTC (rev 6667)
+++ 
gnuradio/branches/developers/gnychis/inband/usrp/host/lib/inband/usrp_server.h  
    2007-10-22 06:38:28 UTC (rev 6668)
@@ -51,6 +51,13 @@
   long d_ntx_chan;
   long d_nrx_chan;
 
+  pmt_t d_usrp_dict;
+
+  bool d_fpga_debug;
+  
+  long d_interp_tx;
+  long d_decim_rx;
+
   // Keep track of the request IDs
   struct rid_info {
     pmt_t owner;
@@ -114,6 +121,8 @@
   bool check_valid(mb_port_sptr port, long channel, std::vector<struct 
channel_info> &chan_info, pmt_t signal_info);
   void parse_control_pkt(pmt_t invocation_handle, transport_pkt *pkt);
   long next_rid();
+  void initialize_registers();
+  void set_register(long reg, long val);
 };
 
 #endif /* INCLUDED_USRP_SERVER_H */