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[Commit-gnuradio] r6771 - gnuradio/branches/developers/jcorgan/t195/usrp
From: |
matt |
Subject: |
[Commit-gnuradio] r6771 - gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib |
Date: |
Thu, 1 Nov 2007 02:10:04 -0600 (MDT) |
Author: matt
Date: 2007-11-01 02:10:04 -0600 (Thu, 01 Nov 2007)
New Revision: 6771
Modified:
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
Log:
hopefully fixes the Glitsch glitch, bug #195. Needs debug pins assigned.
Modified:
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
2007-11-01 05:19:52 UTC (rev 6770)
+++ gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
2007-11-01 08:10:04 UTC (rev 6771)
@@ -20,21 +20,24 @@
//
// Interface to Cypress FX2 bus
-// A packet is 512 Bytes. Each fifo line is 2 bytes
-// Fifo has 1024 or 2048 lines
+// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer
- ( input usbclk,
- input bus_reset, // Not used in RX
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
+ ( // Read/USB side
+ input usbclk,
+ input bus_reset,
output [15:0] usbdata,
input RD,
- output wire have_pkt_rdy,
+ output reg have_pkt_rdy,
output reg rx_overrun,
+ input clear_status,
+ // Write/DSP side
+ input rxclk,
+ input reset, // DSP side reset (used here), do not reset registers
+ input rxstrobe,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
@@ -44,74 +47,91 @@
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
+ // Settings, on rxclk also
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+ input reset_regs, //Only reset registers
output [15:0] debugbus
);
-
- wire [15:0] fifodata, fifodata_8;
- reg [15:0] fifodata_16;
- wire [11:0] rxfifolevel;
- wire rx_empty, rx_full;
-
- wire bypass_hb, want_q;
- wire [4:0] bitwidth;
- wire [3:0] bitshift;
+ wire [15:0] fifodata, fifodata_8;
+ reg [15:0] fifodata_16;
+ wire [11:0] rxfifolevel;
+ wire rx_full;
+
+ wire bypass_hb, want_q;
+ wire [4:0] bitwidth;
+ wire [3:0] bitshift;
+
setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({bypass_hb,want_q,bitwidth,bitshift}));
- // Receive FIFO (ADC --> USB)
+ // USB Read Side of FIFO
+ always @(negedge usbclk)
+ have_pkt_rdy <= (rxfifolevel >= 256);
// 257 Bug Fix
- reg [8:0] read_count;
+ reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
+ read_count <= 0;
+ else if(RD)
+ read_count <= read_count + 1;
else
- read_count <= #1 RD ? read_count : 9'b0;
+ read_count <= 0;
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rxstrobe & (store_next != 0))
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ // FIFO
+ wire ch0_in, ch0_out, iq_out;
+ assign ch0_in = (phase == 1);
- reg [3:0] store_next;
+ fifo_4k_18 rxfifo
+ ( // DSP Write Side
+ .data ( {ch0_in, phase[0], fifodata} ),
+ .wrreq (~rx_full & (phase != 0)),
+ .wrclk ( rxclk ),
+ .wrfull ( rx_full ),
+ .wrempty ( ),
+ .wrusedw ( ),
+ // USB Read Side
+ .q ( {ch0_out,iq_out,usbdata} ),
+ .rdreq ( RD & ~read_count[8] ),
+ .rdclk ( ~usbclk ),
+ .rdfull ( ),
+ .rdempty ( ),
+ .rdusedw ( rxfifolevel ),
+ // Async, shared
+ .aclr ( reset ) );
+
+ // DSP Write Side of FIFO
+ reg [3:0] phase;
always @(posedge rxclk)
if(reset)
- store_next <= #1 4'd0;
- else if(rxstrobe & (store_next == 0))
- store_next <= #1 4'd1;
- else if(~rx_full & (store_next == channels))
- store_next <= #1 4'd0;
- else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1)))
- store_next <= #1 4'd0;
- else if(~rx_full & (store_next != 0))
- store_next <= #1 store_next + 4'd1;
-
+ phase <= 4'd0;
+ else if(phase == 0)
+ begin
+ if(rxstrobe)
+ phase <= 4'd1;
+ end
+ else if(~rx_full)
+ if(phase == channels)
+ phase <= 4'd0;
+ else
+ phase <= phase + 4'd1;
+
assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
-
+
assign fifodata_8 = {round_8(top),round_8(bottom)};
reg [15:0] top,bottom;
-
+
function [7:0] round_8;
input [15:0] in_val;
-
+
round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
endfunction // round_8
always @*
- case(store_next)
+ case(phase)
4'd1 : begin
bottom = ch_0;
top = ch_1;
@@ -132,10 +152,10 @@
top = 16'hFFFF;
bottom = 16'hFFFF;
end
- endcase // case(store_next)
+ endcase // case(phase)
always @*
- case(store_next)
+ case(phase)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
4'd3 : fifodata_16 = ch_2;
@@ -145,28 +165,25 @@
4'd7 : fifodata_16 = ch_6;
4'd8 : fifodata_16 = ch_7;
default : fifodata_16 = 16'hFFFF;
- endcase // case(store_next)
+ endcase // case(phase)
- fifo_4k rxfifo
- ( .data ( fifodata ),
- .wrreq (~rx_full & (store_next != 0)),
- .wrclk ( rxclk ),
+ // Detect overrun
+ reg clear_status_dsp, rx_overrun_dsp;
+ always @(posedge rxclk)
+ clear_status_dsp <= clear_status;
- .q ( usbdata ),
- .rdreq ( RD & ~read_count[8] ),
- .rdclk ( ~usbclk ),
-
- .aclr ( reset ), // This one is asynchronous, so we can use either
reset
-
- .rdempty ( rx_empty ),
- .rdusedw ( rxfifolevel ),
- .wrfull ( rx_full ),
- .wrusedw ( )
- );
-
- assign have_pkt_rdy = (rxfifolevel >= 256);
+ always @(negedge usbclk)
+ rx_overrun <= rx_overrun_dsp;
- // Debugging Aids
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun_dsp <= 1'b0;
+ else if(rxstrobe & (phase != 0))
+ rx_overrun_dsp <= 1'b1;
+ else if(clear_status_dsp)
+ rx_overrun_dsp <= 1'b0;
+
+ // RX Debug Bus
assign debugbus[0] = RD;
assign debugbus[1] = rx_overrun;
assign debugbus[2] = read_count[8];
@@ -174,9 +191,8 @@
assign debugbus[4] = rxstrobe;
assign debugbus[5] = usbclk;
assign debugbus[6] = have_pkt_rdy;
- assign debugbus[10:7] = store_next;
- //assign debugbus[15:11] = rxfifolevel[4:0];
- assign debugbus[15:11] = bitwidth;
+ assign debugbus[10:7] = phase;
+ assign debugbus[15:11] = rxfifolevel[4:0];
endmodule // rx_buffer
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